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Date:   Thu, 24 Oct 2019 03:07:30 -0400
From:   Brian Masney <masneyb@onstation.org>
To:     Georgi Djakov <georgi.djakov@linaro.org>
Cc:     agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org,
        mark.rutland@arm.com, linux-arm-msm@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 5/5] ARM: dts: qcom: msm8974: add interconnect nodes
Message-ID: <20191024070730.GA19974@onstation.org>
References: <20191013080804.10231-1-masneyb@onstation.org>
 <20191013080804.10231-6-masneyb@onstation.org>
 <d154b0c6-fc39-bebc-d1b5-cc179fb6055d@linaro.org>
 <20191023124753.GA14218@onstation.org>
 <c26159f5-e6fe-07f1-51b3-50b72b258846@linaro.org>
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On Wed, Oct 23, 2019 at 04:39:21PM +0300, Georgi Djakov wrote:
> On 23.10.19 г. 15:47 ч., Brian Masney wrote:
> > On Wed, Oct 23, 2019 at 02:50:19PM +0300, Georgi Djakov wrote:
> >> On 13.10.19 г. 11:08 ч., Brian Masney wrote:
> >>> Add interconnect nodes that's needed to support bus scaling.
> >>>
> >>> Signed-off-by: Brian Masney <masneyb@onstation.org>
> >>> ---
> >>>  arch/arm/boot/dts/qcom-msm8974.dtsi | 60 +++++++++++++++++++++++++++++
> >>>  1 file changed, 60 insertions(+)
> >>>
> >>> diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
> >>> @@ -1152,6 +1207,11 @@
> >>>  				              "core",
> >>>  				              "vsync";
> >>>  
> >>> +				interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
> >>> +				                <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
> >>
> >> Who will be the requesting bandwidth to DDR and ocmem? Is it the display or GPU
> >> or both? The above seem like GPU-related interconnects, so maybe these
> >> properties should be in the GPU DT node.
> > 
> > The display is what currently requests the interconnect path,
> > specifically mdp5_setup_interconnect() in
> > drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c. The Freedreno GPU bindings
> > currently don't have interconnect support. Maybe this is something that
> > I should add to that driver as well?
> 
> The "mdp0-mem" and "mdp1-mem" paths mentioned in the mdp5_kms.c are the two
> interconnects between the display and DDR memory.

OK, I see. Most of the interconnect paths in the downstream MSM 3.4
sources are configured in device tree using the
qcom,msm-bus,vectors-KBps property, which is what I was only looking at
before. The interconnect path for the display is configured directly in
code (drivers/video/msm/mdss/mdss_mdp.c) to setup a path between
MSM_BUS_MASTER_MDP_PORT0 and MSM_BUS_SLAVE_EBI_CH0.

In the upstream kernel, it looks like I'll need to

  1) add support for an optional second interconnect path for ocmem to
     drivers/gpu/drm/msm/adreno/adreno_gpu.c.

  2) add implementations of gpu_get_freq and gpu_get_freq to the
     adreno_gpu_funcs struct in drivers/gpu/drm/msm/adreno/a3xx_gpu.c.

Brian