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Thu, 24 Oct 2019 00:05:39 -0700 Received: from xsj-pvapsmtp01 (mailhub.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id x9O75WMa007727; Thu, 24 Oct 2019 00:05:32 -0700 Received: from [172.30.17.123] by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iNXBc-0001VL-4J; Thu, 24 Oct 2019 00:05:32 -0700 Subject: Re: [PATCH] ARM: dts: zynq: enablement of coresight topology To: Mathieu Poirier , Michal Simek Cc: Linux Kernel Mailing List , Michal Simek , git@xilinx.com, Zumeng Chen , Quanyang Wang , Mark Rutland , Peter Crosthwaite , Rob Herring , Rob Herring , Rob Herring , Steffen Trumtrar , devicetree@vger.kernel.org, linux-arm-kernel , u-boot@lists.denx.de References: From: Michal Simek Message-ID: <5100bc31-66b4-f892-7916-d049e6e5d668@xilinx.com> Date: Thu, 24 Oct 2019 09:05:28 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(39850400004)(136003)(396003)(376002)(346002)(189003)(199004)(6246003)(76176011)(336012)(426003)(23676004)(2486003)(58126008)(356004)(6666004)(26005)(31696002)(126002)(230700001)(305945005)(31686004)(486006)(186003)(446003)(11346002)(2906002)(2616005)(476003)(106002)(5660300002)(70586007)(70206006)(36756003)(7416002)(36386004)(65806001)(4326008)(81156014)(65956001)(81166006)(478600001)(47776003)(9786002)(8676002)(8936002)(110136005)(316002)(54906003)(50466002)(44832011)(229853002);DIR:OUT;SFP:1101;SCL:1;SRVR:DM5PR02MB2380;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: aa110766-7f84-417b-7e1c-08d7585096d5 X-MS-TrafficTypeDiagnostic: DM5PR02MB2380: X-LD-Processed: 657af505-d5df-48d0-8300-c31994686c5c,ExtAddr X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-Forefront-PRVS: 0200DDA8BE X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zkKDO5RY7hTLDdilU5pnW8FcX4o3A4zsaw4S/GOikdodM0X9tIhNZ8EVtlUMG4FU4oKQlf9IEs4++TIhiUp8g2LqutXPePHP89nYPyOUlpmwRfxx+RdASc4YC9ogdcNyLwl9CS9Jp2htnM2DrAtHO4oVS3m5WAYUIO2jZIBB4myGwf9ec3JrVdbFgfBiMkjY3jDYmKOYYuUG9zHikoHSPahIa3skS0bnxGaOtWAHMlAH1YxVJSaflQ3Vnbo6fyPhy+8wvCacEnee6juFYDsuxYo+We1zjQOV6VS5a6Ne4Iqp+S0rb1XJuImWFx+KYKOZ9QTDTmrMS3sVFJus2tB+hTBcJj9KqXKk+D1cEVnVjyC1ES1oTcHTWkygR4q142z1t2XO6Tf6g5r/zXqBNI6R5sgACMDJR0fMUpc7XsakHtDp25EFbiVLOmqDfSpcRTg/ X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2019 07:05:44.5574 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aa110766-7f84-417b-7e1c-08d7585096d5 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB2380 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mathieu, On 23. 10. 19 19:32, Mathieu Poirier wrote: > Hi Michal, > > I was not CC'ed on the original post so I just noticed this today, > hence the late reply. I don't know if you were looking for feedback > or already picked up the patch but here it is anyway. I haven't put the patch to my zynq/dt branch yet. And definitely any feedback on this is welcome. > > On Wed, 9 Oct 2019 at 08:07, Michal Simek wrote: >> >> From: Zumeng Chen >> >> This patch is to build the coresight topology structure of zynq-7000 >> series according to the docs of coresight and userguide of zynq-7000. >> >> Signed-off-by: Zumeng Chen >> Signed-off-by: Quanyang Wang >> Signed-off-by: Michal Simek >> --- >> >> arch/arm/boot/dts/zynq-7000.dtsi | 158 +++++++++++++++++++++++++++++++ >> 1 file changed, 158 insertions(+) >> >> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi >> index ca6425ad794c..86430ad76fee 100644 >> --- a/arch/arm/boot/dts/zynq-7000.dtsi >> +++ b/arch/arm/boot/dts/zynq-7000.dtsi >> @@ -59,6 +59,40 @@ >> regulator-always-on; >> }; >> >> + replicator { >> + compatible = "arm,coresight-static-replicator"; >> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; >> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; >> + >> + out-ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + /* replicator output ports */ >> + port@0 { >> + reg = <0>; >> + replicator_out_port0: endpoint { >> + remote-endpoint = <&tpiu_in_port>; >> + }; >> + }; >> + port@1 { >> + reg = <1>; >> + replicator_out_port1: endpoint { >> + remote-endpoint = <&etb_in_port>; >> + }; >> + }; >> + }; >> + in-ports { >> + /* replicator input port */ >> + port { >> + replicator_in_port0: endpoint { >> + slave-mode; > > The slave-mode property is no longer required and probably an > oversight since it doesn't appear elsewhere in this patch. likely yes. I will remove it. > >> + remote-endpoint = <&funnel_out_port>; >> + }; >> + }; >> + }; >> + }; >> + >> amba: amba { >> compatible = "simple-bus"; >> #address-cells = <1>; >> @@ -365,5 +399,129 @@ >> reg = <0xf8005000 0x1000>; >> timeout-sec = <10>; >> }; >> + >> + etb@f8801000 { >> + compatible = "arm,coresight-etb10", "arm,primecell"; >> + reg = <0xf8801000 0x1000>; >> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; >> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; >> + in-ports { >> + port { >> + etb_in_port: endpoint { >> + remote-endpoint = <&replicator_out_port1>; >> + }; >> + }; >> + }; >> + }; >> + >> + tpiu@f8803000 { >> + compatible = "arm,coresight-tpiu", "arm,primecell"; >> + reg = <0xf8803000 0x1000>; >> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; >> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; >> + in-ports { >> + port { >> + tpiu_in_port: endpoint { >> + remote-endpoint = <&replicator_out_port0>; >> + }; >> + }; >> + }; >> + }; >> + >> + funnel@f8804000 { >> + compatible = "arm,coresight-static-funnel", "arm,primecell"; >> + reg = <0xf8804000 0x1000>; >> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; >> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; >> + >> + /* funnel output ports */ >> + out-ports { >> + port { >> + funnel_out_port: endpoint { >> + remote-endpoint = >> + <&replicator_in_port0>; >> + }; >> + }; >> + }; >> + >> + in-ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + /* funnel input ports */ >> + port@0 { >> + reg = <0>; >> + funnel0_in_port0: endpoint { >> + remote-endpoint = <&ptm0_out_port>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + funnel0_in_port1: endpoint { >> + remote-endpoint = <&ptm1_out_port>; >> + }; >> + }; >> + >> + port@2 { >> + reg = <2>; >> + funnel0_in_port2: endpoint { >> + }; >> + }; >> + >> + port@3 { >> + reg = <3>; >> + funnel0_in_port3: endpoint { >> + remote-endpoint = <&itm_out_port>; >> + }; >> + }; >> + /* The other input ports are not connect to anything */ >> + }; >> + }; >> + >> + /* ITM is not supported by kernel, only leave device node here */ >> + itm@f8805000 { >> + compatible = "arm,coresight-etm3x", "arm,primecell"; > > If I remember correctly ITM and ETMv3 are quite different - please > remove entirely. This was commented already. Definitely "arm,coresight-etm3x" should be removed. arm,primecell could stay there. Do you think that make sense to remove it completely because I expect that connection to funnel should be aligned with others. > >> + reg = <0xf8805000 0x1000>; >> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; >> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; >> + out-ports { >> + port { >> + itm_out_port: endpoint { >> + remote-endpoint = <&funnel0_in_port3>; >> + }; >> + }; >> + }; >> + }; >> + >> + ptm@f889c000 { >> + compatible = "arm,coresight-etm3x", "arm,primecell"; >> + reg = <0xf889c000 0x1000>; >> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; >> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; >> + cpu = <&cpu0>; >> + out-ports { >> + port { >> + ptm0_out_port: endpoint { >> + remote-endpoint = <&funnel0_in_port0>; >> + }; >> + }; >> + }; >> + }; >> + >> + ptm@f889d000 { >> + compatible = "arm,coresight-etm3x", "arm,primecell"; >> + reg = <0xf889d000 0x1000>; >> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; >> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; >> + cpu = <&cpu1>; >> + out-ports { >> + port { >> + ptm1_out_port: endpoint { >> + remote-endpoint = <&funnel0_in_port1>; >> + }; >> + }; >> + }; >> + }; > > With the above: > > Reviewed-by: Mathieu Poirier Let's discuss that ITM part first and definitely thanks for review. Thanks, Michal