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received-spf: None (protection.outlook.com: sifive.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: R14XsCdg+0ZuuHNGotPUvAdOQOL14p72B8/gbBsZpx0eemRutZ+KWeBN5aJWCampBt+N00Txhi26VpPC7IOKCcxMemqXsYPg0vxLn969Vo9LJ8HszSCoKRgtCLM1vm8WQazbWq5/nc8UZQMMfrmpXPbAubfJDVqhdXANxb4iceaJCGMOKElMUB5vee6g9in2PfsDQ4pBz5u4qsdIotKghK80maAJf1lmzoly1VQgujw8kWPtsSiMcWh2+3r3kO6+vaExW8Z3ClDR0Rfe3VeON9J53IDrpQKiLBpxn+AnD2/ngOjSwjS/nNMAemBwcb89rE2pjqIiJvOpJbDRWc6vAL1myHbV782B1WOFhWya143Atvq5zgVVfkIDMIPi8BwbVImSKcZNppWsUdhdo4Pi+uPnKb5qzb64UgPGjoF3+tA0fm3KDjZD1ZYofRjC5ojM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: f26306f8-56c6-4dd0-8f2c-08d758628b19 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Oct 2019 09:14:16.2760 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: w9llapR8GFzKMMbBPXusp0cl42wlUKE4zFEP4CPs4bX5HjgHfkoJ/+RbK0pHOCmqAKkTmTzS1qWPdjLeeup6CQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR13MB3399 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For I/O BARs to work correctly on RISC-V Linux, we need to establish a reserved memory region for them, so that drivers that wish to use I/O BARs can issue reads and writes against a memory region that is mapped to the host PCIe controller's I/O BAR MMIO mapping. Signed-off-by: Yash Shah --- arch/riscv/include/asm/io.h | 7 +++++++ arch/riscv/include/asm/pgtable.h | 7 ++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index fc1189a..3ba4d93 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -13,6 +13,7 @@ =20 #include #include +#include =20 extern void __iomem *ioremap(phys_addr_t offset, unsigned long size); =20 @@ -162,6 +163,12 @@ static inline u64 __raw_readq(const volatile void __io= mem *addr) #endif =20 /* + * I/O port access constants. + */ +#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1) +#define PCI_IOBASE ((void __iomem *)PCI_IO_START) + +/* * Emulation routines for the port-mapped IO space used by some PCI driver= s. * These are defined as being "fully synchronous", but also "not guarantee= d to * be fully ordered with respect to other memory and I/O operations". We'= re diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index 7fc5e4a..d78cc74 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -7,6 +7,7 @@ #define _ASM_RISCV_PGTABLE_H =20 #include +#include =20 #include =20 @@ -88,6 +89,7 @@ extern pgd_t swapper_pg_dir[]; #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) #define VMALLOC_END (PAGE_OFFSET - 1) #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) +#define PCI_IO_SIZE SZ_16M =20 /* * Roughly size the vmemmap space to be large enough to fit enough @@ -102,7 +104,10 @@ extern pgd_t swapper_pg_dir[]; =20 #define vmemmap ((struct page *)VMEMMAP_START) =20 -#define FIXADDR_TOP (VMEMMAP_START) +#define PCI_IO_END VMEMMAP_START +#define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) +#define FIXADDR_TOP PCI_IO_START + #ifdef CONFIG_64BIT #define FIXADDR_SIZE PMD_SIZE #else --=20 2.7.4