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Subject: Re: [PATCH 2/4] i2c: at91: implement i2c bus recovery
To:     Wolfram Sang <wsa@the-dreams.de>, Codrin.Ciubotariu@microchip.com
Cc:     kamel.bouhara@bootlin.com, linux-arm-kernel@lists.infradead.org,
        linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org,
        Nicolas.Ferre@microchip.com, alexandre.belloni@bootlin.com,
        Ludovic.Desroches@microchip.com, devicetree@vger.kernel.org,
        thomas.petazzoni@bootlin.com
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From:   Phil Reid <preid@electromag.com.au>
Message-ID: <65d83bb0-9a0c-c6e2-1c58-cb421c69816c@electromag.com.au>
Date:   Fri, 25 Oct 2019 09:14:00 +0800
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On 24/10/2019 23:07, Wolfram Sang wrote:
> 
>> So at the beginning of a new transfer, we should check if SDA (or SCL?)
>> is low and, if it's true, only then we should try recover the bus.
> 
> Yes, this is the proper time to do it. Remember, I2C does not define a
> timeout.
> 

FYI: Just a single poll at the start of the transfer, for it being low, will cause problems with multi-master buses.
Bus recovery should be attempted after a timeout when trying to communicate, even thou i2c doesn't define a timeout.

I'm trying to fix the designware drivers handling of this at the moment.

-- 
Regards
Phil Reid