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Fri, 25 Oct 2019 07:37:46 +0000 From: Oliver Graute To: "shawnguo@kernel.org" CC: "oliver.graute@gmail.com" , "aisheng.dong@nxp.com" , Oliver Graute , Rob Herring , Mark Rutland , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Li Yang , Pramod Kumar , Manivannan Sadhasivam , Lucas Stach , Anson Huang , Bhaskar Upadhaya , Richard Hu , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: [PATCHv4 1/1] arm64: dts: add basic DTS for imx8qm-rom7720-a1 board Thread-Topic: [PATCHv4 1/1] arm64: dts: add basic DTS for imx8qm-rom7720-a1 board Thread-Index: AQHViwcYXrZQgZ5EqUymCwPt7Nh/2Q== Date: Fri, 25 Oct 2019 07:37:46 +0000 Message-ID: <20191025073657.17593-2-oliver.graute@kococonnector.com> References: <20191025073657.17593-1-oliver.graute@kococonnector.com> In-Reply-To: <20191025073657.17593-1-oliver.graute@kococonnector.com> Accept-Language: de-DE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MRXP264CA0031.FRAP264.PROD.OUTLOOK.COM (2603:10a6:500:14::19) To DB6PR0902MB2072.eurprd09.prod.outlook.com (2603:10a6:6:8::23) authentication-results: spf=none (sender IP is ) smtp.mailfrom=oliver.graute@kococonnector.com; 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received-spf: None (protection.outlook.com: kococonnector.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: jFB5nSBE45QUJbabBO+r8v0jqdYhqzzE0S+RaG1YmbCuBO28Xmwxl//SGalCLI3wql7mVjiYSDu+dTU7Ze+WKu+c1h/pOgXy/6sTTqABTIz9CeZxBcGs5Xlm2jUyeovQMFCN9YwRr6NbtYx8/mhHrOrt2Z9Hq/HeKNfykOX6Ekbqa32xS4FHCjjk1Sygp+VlFrQ2vyKHUOkzaA6Fxhgp2mH2hjKLnsmkqYJQBO1CprUhkzWrmTjRwCqU0fH7rD7az59vRfkP2WyCxCkS1YnlbSxms/myIXdGc5/QeAdjbtsXK2mkk7S9JzpQsfAaPdZ8C7o0u52GtdMzJF518apxo9dD9CvsTMua8g2CQW3CRTF+rwnYMog0+4bTt+eoSaR3tQWFd4+F+iquFbQH31DmUukarICupIGtwv4gJaoLf1g4k6XNl0KaWhs2xMT48nDK Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: kococonnector.com X-MS-Exchange-CrossTenant-Network-Message-Id: 71d7f22c-1e18-4b13-db1f-08d7591e3a9a X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Oct 2019 07:37:46.4501 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 59845429-0644-4099-bd7e-17fba65a2f2b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: EE1nsc6+Vtaa+FGXLEfUtCl7c+42HhuKRTV1m8XX3mF+jqDv22RbXAVmmt+697/PxRnoqyZuJPhCE5osSdC/evCWgQJimbO+PxQF0Cv2v88= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0902MB1671 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add basic dts support for a Advantech iMX8QM Qseven Board Signed-off-by: Oliver Graute --- Changelog: v4: - added reg_usdhc3_vmmc node - added usdhc3 node arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8qm-rom7720-a1.dts | 299 ++++++++++++++++++ 2 files changed, 300 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 93fce8f0c66d..0de6d384b5ea 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -30,5 +30,6 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-nitrogen.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-pico-pi.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-zii-ultra-rmb3.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-zii-ultra-zest.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8qm-rom7720-a1.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-mek.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts b/arch/arm= 64/boot/dts/freescale/imx8qm-rom7720-a1.dts new file mode 100644 index 000000000000..b7b6f96f224c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* +* Copyright 2017-2018 NXP +* Copyright (C) 2019 Oliver Graute +*/ +/dts-v1/; + +#include "imx8qm.dtsi" + +/ { + model =3D "Advantech iMX8QM Qseven series"; + compatible =3D "fsl,imx8qm"; + + board { + compatible =3D "proc-board"; + board-type =3D "ROM-7720_A1"; + board-cpu =3D "iMX8QM"; + }; + + chosen { + bootargs =3D "console=3DttyLP0,115200 earlycon=3Dlpuart32,0x5a060000,115= 200"; + stdout-path =3D &lpuart0; + }; + + cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + /delete-node/ cpu@101; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x00000000 0x80000000 0 0x40000000>; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "sw-3p3-sd1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay =3D <3000>; + enable-active-high; + }; + + reg_usdhc3_vmmc: usdhc3_vmmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "sw-3p3-sd2"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&lsio_gpio4 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + +&lpuart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpuart0>; + status =3D "okay"; +}; + +&fec1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec1>; + phy-mode =3D "rgmii-txid"; + phy-handle =3D <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <4>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&lsio_gpio4 { + status =3D "okay"; +}; + +&lsio_gpio5 { + status =3D "okay"; +}; + +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width =3D <4>; + cd-gpios =3D <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios =3D <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply =3D <®_usdhc2_vmmc>; + status =3D "okay"; +}; + +&usdhc3 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + bus-width =3D <4>; + cd-gpios =3D <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; + wp-gpios =3D <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>; + vmmc-supply =3D <®_usdhc3_vmmc>; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins =3D < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins =3D < + IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins =3D < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins =3D < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins =3D < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins =3D < + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins =3D < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins =3D < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins =3D < + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins =3D < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins =3D < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; +}; --=20 2.17.1