Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
MIME-Version: 1.0
References: <1570695678-42623-1-git-send-email-jianxin.pan@amlogic.com>
 <1570695678-42623-2-git-send-email-jianxin.pan@amlogic.com>
 <20191014173900.GA6886@bogus> <622c7785-8254-5473-6b35-7287830f3c60@amlogic.com>
In-Reply-To: <622c7785-8254-5473-6b35-7287830f3c60@amlogic.com>
From:   Rob Herring <robh@kernel.org>
Date:   Fri, 25 Oct 2019 15:19:35 -0500
Message-ID: <CAL_Jsq+F9EGv2jEWw2BrmH0NDKMRt6=pG6LSHL8UYH9G+-OeMw@mail.gmail.com>
Subject: Re: [PATCH RESEND v2 1/4] dt-bindings: power: add Amlogic secure
 power domains bindings
To:     Jianxin Pan <jianxin.pan@amlogic.com>
Cc:     Kevin Hilman <khilman@baylibre.com>,
        "open list:ARM/Amlogic Meson..." <linux-amlogic@lists.infradead.org>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Jerome Brunet <jbrunet@baylibre.com>,
        Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
        "open list:THERMAL" <linux-pm@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@lists.infradead.org>, devicetree@vger.kernel.org,
        Jian Hu <jian.hu@amlogic.com>,
        Hanjie Lin <hanjie.lin@amlogic.com>,
        Victor Wan <victor.wan@amlogic.com>,
        Xingyu Chen <xingyu.chen@amlogic.com>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On Wed, Oct 16, 2019 at 6:26 AM Jianxin Pan <jianxin.pan@amlogic.com> wrote=
:
>
> Hi Rob,
>
> On 2019/10/15 1:39, Rob Herring wrote:
> > On Thu, Oct 10, 2019 at 04:21:15AM -0400, Jianxin Pan wrote:
> >> Add the bindings for the Amlogic Secure power domains, controlling the
> >> secure power domains.
> >>
> >> The bindings targets the Amlogic A1 and C1 compatible SoCs, in which t=
he
> >> power domain registers are in secure world.
> >>
> >> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
> >> ---
> >>  .../bindings/power/amlogic,meson-sec-pwrc.yaml     | 42 +++++++++++++=
+++++++++
> >>  include/dt-bindings/power/meson-a1-power.h         | 32 +++++++++++++=
++++
> >>  2 files changed, 74 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/power/amlogic,me=
son-sec-pwrc.yaml
> >> +
> >> +  secure-monitor:
> >> +    description: phandle to the secure-monitor node
> >> +    $ref: /schemas/types.yaml#/definitions/phandle
> >
> > Why not just a child node of this node?
> >
> Thanks for the review.
>
> I followed the style of the previous series of meson=EF=BC=9A
>
>   46         efuse: efuse {
>   47                 compatible =3D "amlogic,meson-gxbb-efuse";
>   48                 clocks =3D <&clkc CLKID_EFUSE>;
>   49                 #address-cells =3D <1>;
>   50                 #size-cells =3D <1>;
>   51                 read-only;
>   52                 secure-monitor =3D <&sm>;
>   53         };

Looks like that was not reviewed by me and is only in linux-next.
Please make functions exposed by secure world a child of the secure
firmware node.

Really for power domains, you only need to add a '#power-domain-cells'
property to the secure monitor node.

Rob