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Date:   Sat, 26 Oct 2019 19:55:25 +0800
From:   Shawn Guo <shawnguo@kernel.org>
To:     Andrey Smirnov <andrew.smirnov@gmail.com>
Cc:     linux-arm-kernel@lists.infradead.org,
        Fabio Estevam <festevam@gmail.com>,
        Chris Healy <cphealy@gmail.com>,
        Lucas Stach <l.stach@pengutronix.de>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/4] arm64: dts: zii-ultra: Add node for accelerometer
Message-ID: <20191026115524.GJ14401@dragon>
References: <20191015152654.26726-1-andrew.smirnov@gmail.com>
 <20191015152654.26726-3-andrew.smirnov@gmail.com>
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On Tue, Oct 15, 2019 at 08:26:53AM -0700, Andrey Smirnov wrote:
> Add I2C node for accelerometer present on both Zest and RMB3 boards.
> 
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Chris Healy <cphealy@gmail.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org,
> Cc: linux-kernel@vger.kernel.org
> ---
>  .../boot/dts/freescale/imx8mq-zii-ultra.dtsi   | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
> index 21eb52341ba8..8395c5a73ba6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
> @@ -262,6 +262,18 @@
>  	pinctrl-0 = <&pinctrl_i2c1>;
>  	status = "okay";
>  
> +	accel@1c {

s/accel/accelerometer

I fixed it up and applied the series.

Shawn

> +		compatible = "fsl,mma8451";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_accel>;
> +		reg = <0x1c>;
> +		interrupt-parent = <&gpio3>;
> +		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
> +		interrupt-names = "INT2";
> +		vdd-supply = <&reg_gen_3p3>;
> +		vddio-supply = <&reg_gen_3p3>;
> +	};
> +
>  	ucs1002: charger@32 {
>  		compatible = "microchip,ucs1002";
>  		pinctrl-names = "default";
> @@ -522,6 +534,12 @@
>  };
>  
>  &iomuxc {
> +	pinctrl_accel: accelgrp {
> +		fsl,pins = <
> +			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20		0x41
> +		>;
> +	};
> +
>  	pinctrl_fec1: fec1grp {
>  		fsl,pins = <
>  			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
> -- 
> 2.21.0
>