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[209.85.221.44]) by smtp.gmail.com with ESMTPSA id s20sm583170edq.44.2019.10.28.18.09.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Oct 2019 18:09:49 -0700 (PDT) Received: by mail-wr1-f44.google.com with SMTP id n15so11773212wrw.13; Mon, 28 Oct 2019 18:09:49 -0700 (PDT) X-Received: by 2002:a05:6000:1252:: with SMTP id j18mr16938815wrx.23.1572311389338; Mon, 28 Oct 2019 18:09:49 -0700 (PDT) MIME-Version: 1.0 References: <20191028214914.3465156-1-megous@megous.com> In-Reply-To: <20191028214914.3465156-1-megous@megous.com> From: Chen-Yu Tsai Date: Tue, 29 Oct 2019 09:09:40 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [linux-sunxi] [PATCH] ARM: sunxi: Fix CPU powerdown on A83T To: =?UTF-8?Q?Ond=C5=99ej_Jirman?= Cc: linux-sunxi , stable , Maxime Ripard , Russell King , "moderated list:ARM/Allwinner sunXi SoC support" , open list Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 29, 2019 at 5:49 AM Ondrej Jirman wrote: > > PRCM_PWROFF_GATING_REG has CPU0 at bit 4 on A83T. So without this > patch, instead of gating the CPU0, the whole cluster was power gated, > when shutting down first CPU in the cluster. > > Fixes: 6961275e72a8c1 ("ARM: sun8i: smp: Add support for A83T") > Signed-off-by: Ondrej Jirman > Cc: stable@vger.kernel.org Acked-by: Chen-Yu Tsai Though I distinctly remember the BSP had some code dealing with chip revisions in which the two bits were reversed. :(