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Tue, 29 Oct 2019 11:16:59 +0000 From: To: , , , CC: , , Subject: [PATCH v3 07/32] mtd: spi-nor: Don't overwrite errno from Reg Ops Thread-Topic: [PATCH v3 07/32] mtd: spi-nor: Don't overwrite errno from Reg Ops Thread-Index: AQHVjkphLyVSrUAb9kyKn0dz1sgAkQ== Date: Tue, 29 Oct 2019 11:16:59 +0000 Message-ID: <20191029111615.3706-8-tudor.ambarus@microchip.com> References: <20191029111615.3706-1-tudor.ambarus@microchip.com> In-Reply-To: <20191029111615.3706-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: LO2P265CA0376.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:a3::28) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [83.166.207.93] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 6a11ebe0-6295-4857-9289-08d75c6183f0 x-ms-traffictypediagnostic: MN2PR11MB3823: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1360; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 6a11ebe0-6295-4857-9289-08d75c6183f0 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Oct 2019 11:16:59.3257 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pu9f9vkJGFXBr0HhXMfAna8/rRDsqwSHvuIxEQJVnJ8obcx/ooYfN4xIY03ghjKV5xr1CS1PFxxPforGz89U188UrsploGjFvbuVxDIcbOM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3823 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Do not overwrite the error numbers received the Register Operations methods. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index c794eff69fe9..1a00438fd061 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1364,10 +1364,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struc= t erase_info *instr) =20 spi_nor_write_enable(nor); =20 - if (spi_nor_erase_chip(nor)) { - ret =3D -EIO; + ret =3D spi_nor_erase_chip(nor); + if (ret) goto erase_err; - } =20 /* * Scale the timeout linearly with the size of the flash, with @@ -1839,7 +1838,7 @@ static int spansion_no_read_cr_quad_enable(struct spi= _nor *nor) ret =3D spi_nor_read_sr(nor); if (ret < 0) { dev_err(nor->dev, "error while reading status register\n"); - return -EINVAL; + return ret; } sr_cr[0] =3D ret; sr_cr[1] =3D CR_QUAD_EN_SPAN; @@ -1870,7 +1869,7 @@ static int spansion_read_cr_quad_enable(struct spi_no= r *nor) ret =3D spi_nor_read_cr(nor); if (ret < 0) { dev_err(dev, "error while reading configuration register\n"); - return -EINVAL; + return ret; } =20 if (ret & CR_QUAD_EN_SPAN) @@ -1882,7 +1881,7 @@ static int spansion_read_cr_quad_enable(struct spi_no= r *nor) ret =3D spi_nor_read_sr(nor); if (ret < 0) { dev_err(dev, "error while reading status register\n"); - return -EINVAL; + return ret; } sr_cr[0] =3D ret; =20 @@ -1932,7 +1931,7 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) ret =3D spi_nor_write_sr2(nor, sr2); if (ret) { dev_err(nor->dev, "error while writing status register 2\n"); - return -EINVAL; + return ret; } =20 ret =3D spi_nor_wait_till_ready(nor); --=20 2.9.5