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Date:   Tue, 29 Oct 2019 16:02:43 +0100
From:   Peter Zijlstra <peterz@infradead.org>
To:     Luwei Kang <luwei.kang@intel.com>
Cc:     kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
        pbonzini@redhat.com, rkrcmar@redhat.com,
        sean.j.christopherson@intel.com, vkuznets@redhat.com,
        wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org,
        tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com,
        x86@kernel.org, ak@linux.intel.com, thomas.lendacky@amd.com,
        acme@kernel.org, mark.rutland@arm.com,
        alexander.shishkin@linux.intel.com, jolsa@redhat.com,
        namhyung@kernel.org
Subject: Re: [PATCH v1 2/8] KVM: x86: PEBS output to Intel PT MSRs emulation
Message-ID: <20191029150243.GM4097@hirez.programming.kicks-ass.net>
References: <1572217877-26484-1-git-send-email-luwei.kang@intel.com>
 <1572217877-26484-3-git-send-email-luwei.kang@intel.com>
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On Sun, Oct 27, 2019 at 07:11:11PM -0400, Luwei Kang wrote:
> Intel new hardware introduces a mechanism to direct PEBS records
> output into the Intel PT buffer that can be used for enabling PEBS
> in KVM guest. This patch implements the registers read and write
> emulation when PEBS is supported in KVM guest.
> 
> KMM needs to reprogram the counters when the value of these MSRs
> be changed that to make sure it can take effect in hardware.
> 
> Signed-off-by: Luwei Kang <luwei.kang@intel.com>
> ---
>  arch/x86/include/asm/kvm_host.h  |  4 +++
>  arch/x86/include/asm/msr-index.h |  6 ++++
>  arch/x86/kvm/vmx/capabilities.h  | 15 ++++++++++
>  arch/x86/kvm/vmx/pmu_intel.c     | 63 ++++++++++++++++++++++++++++++++++++++--
>  4 files changed, 86 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 20ce682..d22f8d9 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -131,9 +131,13 @@
>  #define LBR_INFO_ABORT			BIT_ULL(61)
>  #define LBR_INFO_CYCLES			0xffff
>  
> +#define MSR_IA32_PEBS_PMI_AFTER_REC	BIT_ULL(60)
> +#define MSR_IA32_PEBS_OUTPUT_PT		BIT_ULL(61)
> +#define MSR_IA32_PEBS_OUTPUT_MASK	(3ULL << 61)
>  #define MSR_IA32_PEBS_ENABLE		0x000003f1
>  #define MSR_PEBS_DATA_CFG		0x000003f2
>  #define MSR_IA32_DS_AREA		0x00000600
> +#define MSR_IA32_PERF_CAP_PEBS_OUTPUT_PT	BIT_ULL(16)
>  #define MSR_IA32_PERF_CAPABILITIES	0x00000345
>  #define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
>  
> @@ -665,6 +669,8 @@
>  #define MSR_IA32_MISC_ENABLE_FERR			(1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
>  #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT		10
>  #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX		(1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
> +#define MSR_IA32_MISC_ENABLE_PEBS_BIT			12
> +#define MSR_IA32_MISC_ENABLE_PEBS			(1ULL << MSR_IA32_MISC_ENABLE_PEBS_BIT)
>  #define MSR_IA32_MISC_ENABLE_TM2_BIT			13
>  #define MSR_IA32_MISC_ENABLE_TM2			(1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
>  #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT	19

Some of these already exist but are local to perf. Don't blindly
introduce more without unifying.