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[209.132.180.67]) by mx.google.com with ESMTP id f3si5080101ejb.49.2019.10.29.13.19.25; Tue, 29 Oct 2019 13:19:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@megous.com header.s=mail header.b=pcOwD97e; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=megous.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727430AbfJ2URr (ORCPT + 99 others); Tue, 29 Oct 2019 16:17:47 -0400 Received: from vps.xff.cz ([195.181.215.36]:37800 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726530AbfJ2URq (ORCPT ); Tue, 29 Oct 2019 16:17:46 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1572380265; bh=ZIeztklJ0KTOmeGymoSca7KVDZDZTYZJ3bIQeMsD8Fs=; h=From:To:Cc:Subject:Date:References:From; b=pcOwD97ewhvRp9CgH0d5PKv1R45tiAXkQNdjpo+KI+C0zUXxaDVGCm4luMfVATQr4 3SRg4i75KfhVZ7pWu7LnvuLKaN6k7ZJSdgHUbaoac+RYEkLidUsBeEr7hrrdPscdEe C/6n5SvdNTeW1NiGuZqUxS/TAIPgoH2Xp36AwKdU= From: Ondrej Jirman To: linux-sunxi@googlegroups.com, Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Icenowy Zheng , Thomas Gleixner , Arnd Bergmann Cc: Greg Kroah-Hartman , Paul Kocialkowski , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ondrej Jirman Subject: [PATCH v3 3/4] arm64: dts: allwinner: h6: add USB3 device nodes Date: Tue, 29 Oct 2019 21:17:40 +0100 Message-Id: <20191029201741.3820913-4-megous@megous.com> In-Reply-To: <20191029201741.3820913-1-megous@megous.com> References: <20191029201741.3820913-1-megous@megous.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Icenowy Zheng Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and a custom PHY. Add device tree nodes for them. Signed-off-by: Ondrej Jirman Signed-off-by: Icenowy Zheng Reviewed-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 32 ++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 5d7ab540b950..9dbe63bf5a77 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -547,6 +547,38 @@ status = "disabled"; }; + dwc3: dwc3@5200000 { + compatible = "snps,dwc3"; + reg = <0x05200000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_XHCI>, + <&ccu CLK_BUS_XHCI>, + <&rtc 0>; + clock-names = "ref", "bus_early", "suspend"; + resets = <&ccu RST_BUS_XHCI>; + /* + * The datasheet of the chip doesn't declare the + * peripheral function, and there's no boards known + * to have a USB Type-B port routed to the port. + * In addition, no one has tested the peripheral + * function yet. + * So set the dr_mode to "host" in the DTSI file. + */ + dr_mode = "host"; + phys = <&usb3phy>; + phy-names = "usb3-phy"; + status = "disabled"; + }; + + usb3phy: phy@5210000 { + compatible = "allwinner,sun50i-h6-usb3-phy"; + reg = <0x5210000 0x10000>; + clocks = <&ccu CLK_USB_PHY1>; + resets = <&ccu RST_USB_PHY1>; + #phy-cells = <0>; + status = "disabled"; + }; + ehci3: usb@5311000 { compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; reg = <0x05311000 0x100>; -- 2.23.0