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From:   "Kang, Luwei" <luwei.kang@intel.com>
To:     Peter Zijlstra <peterz@infradead.org>
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Subject: RE: [PATCH v1 4/8] KVM: x86: Aviod clear the PEBS counter when PEBS
 enabled in guest
Thread-Topic: [PATCH v1 4/8] KVM: x86: Aviod clear the PEBS counter when
 PEBS enabled in guest
Thread-Index: AQHVjLd4hZIWJ8IukEOg3V+5ZZvUU6dxMmCAgAE4tMA=
Date:   Wed, 30 Oct 2019 04:06:42 +0000
Message-ID: <82D7661F83C1A047AF7DC287873BF1E173835B24@SHSMSX104.ccr.corp.intel.com>
References: <1572217877-26484-1-git-send-email-luwei.kang@intel.com>
 <1572217877-26484-5-git-send-email-luwei.kang@intel.com>
 <20191029145553.GL4097@hirez.programming.kicks-ass.net>
In-Reply-To: <20191029145553.GL4097@hirez.programming.kicks-ass.net>
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> > This patch introduce a parameter that avoid clear the PEBS event
> > counter while running in the guest. The performance counter which use
> > for PEBS event can be enabled through VM-entry when PEBS is enabled in
> > guest by PEBS output to Intel PT.
> 
> Please write coherent Changelogs. I have no clue what you're trying to say.
> 
> Also, maybe this attrocious coding style is accepted in KVM, but I'm not having it. Pretty much all your linebreaks and subsequent
> indenting is against style.

Sorry. I mean the performance counter for PEBS event must be disabled before VM-entry at present. After PEBS enabled in guest by PEBS via PT, we don't need to disable the PEBS counters.
We be corrected in next version.

Thanks,
Luwei Kang