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Subject: Re: [PATCH v2 01/14] dt-bindings: phy: Sierra: Add bindings for
 Sierra in TI's J721E
To:     Rob Herring <robh@kernel.org>, Anil Varughese <aniljoy@cadence.com>
CC:     Roger Quadros <rogerq@ti.com>, Jyri Sarha <jsarha@ti.com>,
        <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
References: <20191023125735.4713-1-kishon@ti.com>
 <20191023125735.4713-2-kishon@ti.com> <20191029185916.GA19313@bogus>
From:   Kishon Vijay Abraham I <kishon@ti.com>
Message-ID: <8ec5a9bd-4283-04bf-af4c-c5b7b912a342@ti.com>
Date:   Wed, 30 Oct 2019 11:06:18 +0530
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Hi Rob,

On 30/10/19 12:29 AM, Rob Herring wrote:
> On Wed, Oct 23, 2019 at 06:27:22PM +0530, Kishon Vijay Abraham I wrote:
>> Add DT binding documentation for Sierra PHY IP used in TI's J721E
>> SoC.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>>  .../devicetree/bindings/phy/phy-cadence-sierra.txt  | 13 ++++++++-----
>>  1 file changed, 8 insertions(+), 5 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
>> index 6e1b47bfce43..bf90ef7e005e 100644
>> --- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
>> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
>> @@ -2,21 +2,24 @@ Cadence Sierra PHY
>>  -----------------------
>>  
>>  Required properties:
>> -- compatible:	cdns,sierra-phy-t0
>> -- clocks:	Must contain an entry in clock-names.
>> -		See ../clocks/clock-bindings.txt for details.
>> -- clock-names:	Must be "phy_clk"
>> +- compatible:	Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
>> +		Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
>>  - resets:	Must contain an entry for each in reset-names.
>>  		See ../reset/reset.txt for details.
>>  - reset-names:	Must include "sierra_reset" and "sierra_apb".
>>  		"sierra_reset" must control the reset line to the PHY.
>>  		"sierra_apb" must control the reset line to the APB PHY
>> -		interface.
>> +		interface ("sierra_apb" is optional).
>>  - reg:		register range for the PHY.
>>  - #address-cells: Must be 1
>>  - #size-cells:	Must be 0
>>  
>>  Optional properties:
>> +- clocks:		Must contain an entry in clock-names.
>> +			See ../clocks/clock-bindings.txt for details.
>> +- clock-names:		Must be "phy_clk". Must contain "cmn_refclk" and
>> +			"cmn_refclk1" for configuring the frequency of the
>> +			clock to the lanes.
> 
> I don't understand how the same block can have completely different 
> clocks. Did the original binding forget some? 
> 
> TI needs 0, 1 or 3 clocks? Reads like it could be any.

For TI, phy_clk is not needed. Anil, can you clarify what this clock actually
corresponds to? Is it a functional clock of PHY?

Sierra SERDES actually has a number of clocks which can be configured. The
initial dt-binding didn't model all these clocks. The "cmn_refclk" and
"cmn_refclk1" are used to program the dividers withing the Sierra. The actual
registers for programming the dividers are in the Sierra wrapper though. The
original Sierra driver and dt-binding didn't try to change the default divider
values.

Thanks
Kishon
> 
> Rob
>