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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: Tg/2A49NKh1tqcvZURVhDbm2iQuwtM43yJDNHBoMPaWI0t0TZErjyyTIiKax7Ar20+ys35kX9Z5r74v6+EIOftFCyMe7J+7lqj791OKHkduXowBmidPtvACB1aWLdUdaI0Pi3QNTOn+M4irY3UzHJ5RqNLs/cjl0wlUVvsPefmy6M4lXsu51/Tk1MBleKRksRhneXPJK+qtyhc+K1vgqHBi2KBm8XKZHCfIjtBAMbVNfNVYGFOiQrUW9ocJKFAlH3NSh7qiLwPHBspKan+XBtgZ/6YGcgNoRcDBoWwFJ+bGyUV6fyktTHDtvYJRgUM75SU+VGpdu3XXz/75+i02Mlqg/jqyi92yNwQ1WM2YziGDlLXpUUaQxwVJ9Qj2QiIsuqB+t3igmv/yJ4/qK1KfqqOzb+Wpn9ke+D9pAz88moLepAjM6hiwqh27fWWehgGAq Content-Type: text/plain; charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5581adeb-3d28-4495-0c61-08d75d1c2d1b X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Oct 2019 09:33:09.5788 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 2DQte0/mmYKwM+IruiwBZwpGytFtHE3vXeKaByggSSxBQ7S/ZLYzGGvenzJV7zLqGna/31OMc0vafGTHVzYmeA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB3985 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 19-10-28 16:53:00, Shawn Guo wrote: > @Abel, comments? >=20 Looks good to me. Reviewed-by: Abel Vesa > Shawn >=20 > On Thu, Oct 24, 2019 at 06:57:21AM +0000, Peng Fan wrote: > > From: Peng Fan > >=20 > > The current clk tree shows: > > osc_25m 9 11 0 25000000 = 0 0 50000 > > sys2_pll1_ref_sel 1 1 0 25000000 = 0 0 50000 > > sys3_pll_out 1 1 0 25000000 = 0 0 50000 > > sys1_pll1_ref_sel 2 2 0 25000000 = 0 0 50000 > > sys2_pll_out 6 6 0 1000000000 = 0 0 50000 > >=20 > > It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent, > > sys2_pll_out use sys1_pll1_ref_sel as parent. > >=20 > > According to the current imx_clk_sccg_pll design, it uses both > > bypass1/2, however set bypass2 as 1 is not correct, because it will > > make sys[x]_pll_out use wrong parent and might access wrong registers. > >=20 > > So correct bypass2 to 0 and fix sys2/3_pll_out_sels. > >=20 > > After fix, the tree shows: > > osc_25m 10 12 0 25000000 = 0 0 50000 > > sys3_pll1_ref_sel 1 1 0 25000000 = 0 0 50000 > > sys3_pll_out 1 1 0 25000000 = 0 0 50000 > > sys2_pll1_ref_sel 1 1 0 25000000 = 0 0 50000 > > sys2_pll_out 6 6 0 1000000000 = 0 0 50000 > > sys1_pll1_ref_sel 1 1 0 25000000 = 0 0 50000 > > sys1_pll_out 5 5 0 800000000 = 0 0 50000 > >=20 > > Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk") > > Signed-off-by: Peng Fan > > --- > > drivers/clk/imx/clk-imx8mq.c | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > >=20 > > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.= c > > index 05ece7b5da54..e17f0ebfacb0 100644 > > --- a/drivers/clk/imx/clk-imx8mq.c > > +++ b/drivers/clk/imx/clk-imx8mq.c > > @@ -35,8 +35,8 @@ static const char * const audio_pll2_bypass_sels[] = =3D {"audio_pll2", "audio_pll2_ > > static const char * const video_pll1_bypass_sels[] =3D {"video_pll1", = "video_pll1_ref_sel", }; > > =20 > > static const char * const sys1_pll_out_sels[] =3D {"sys1_pll1_ref_sel"= , }; > > -static const char * const sys2_pll_out_sels[] =3D {"sys1_pll1_ref_sel"= , "sys2_pll1_ref_sel", }; > > -static const char * const sys3_pll_out_sels[] =3D {"sys3_pll1_ref_sel"= , "sys2_pll1_ref_sel", }; > > +static const char * const sys2_pll_out_sels[] =3D {"sys2_pll1_ref_sel"= , }; > > +static const char * const sys3_pll_out_sels[] =3D {"sys3_pll1_ref_sel"= , }; > > static const char * const dram_pll_out_sels[] =3D {"dram_pll1_ref_sel"= , }; > > static const char * const video2_pll_out_sels[] =3D {"video2_pll1_ref_= sel", }; > > =20 > > @@ -345,8 +345,8 @@ static int imx8mq_clocks_probe(struct platform_devi= ce *pdev) > > clks[IMX8MQ_VIDEO_PLL1_OUT] =3D imx_clk_gate("video_pll1_out", "video= _pll1_bypass", base + 0x10, 21); > > =20 > > clks[IMX8MQ_SYS1_PLL_OUT] =3D imx_clk_sccg_pll("sys1_pll_out", sys1_p= ll_out_sels, ARRAY_SIZE(sys1_pll_out_sels), 0, 0, 0, base + 0x30, CLK_IS_CR= ITICAL); > > - clks[IMX8MQ_SYS2_PLL_OUT] =3D imx_clk_sccg_pll("sys2_pll_out", sys2_p= ll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + 0x3c, CLK_IS_CR= ITICAL); > > - clks[IMX8MQ_SYS3_PLL_OUT] =3D imx_clk_sccg_pll("sys3_pll_out", sys3_p= ll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, CLK_IS_CR= ITICAL); > > + clks[IMX8MQ_SYS2_PLL_OUT] =3D imx_clk_sccg_pll("sys2_pll_out", sys2_p= ll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 0, base + 0x3c, CLK_IS_CR= ITICAL); > > + clks[IMX8MQ_SYS3_PLL_OUT] =3D imx_clk_sccg_pll("sys3_pll_out", sys3_p= ll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, base + 0x48, CLK_IS_CR= ITICAL); > > clks[IMX8MQ_DRAM_PLL_OUT] =3D imx_clk_sccg_pll("dram_pll_out", dram_p= ll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CR= ITICAL); > > clks[IMX8MQ_VIDEO2_PLL_OUT] =3D imx_clk_sccg_pll("video2_pll_out", vi= deo2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0= ); > > =20 > > --=20 > > 2.16.4 > >=20