Message-ID: <43C3D350.6070003@microgate.com>
Date: Tue, 10 Jan 2006 09:31:28 -0600
From: Paul Fulghum <paulkf@microgate.com>
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To: =?ISO-8859-1?Q?Burkhard_Sch=F6lpen?= <bschoelpen@web.de>
CC: linux-kernel@vger.kernel.org
Subject: Re: PCI DMA Interrupt latency
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Burkhard Sch?lpen wrote:
> The issue seems to be something like interrupt 
> latency in hardware. Measuring some signals with an 
> oscilloscope shows, that the delay from generating the 
> interrupt, which signals a finished transfer, to the time 
> when the interrupt register on the card is reset (i.e. the 
> beginning of the ISR) sometimes increases to more 
> than 500 microseconds, which is dimensions too high. 
> 
> ... Another consideration is, that 
> another driver could lock all interrupts for too long (but for 
> 500 us??).  

I also have implemented bus master devices based
on the Spartan 2 + Xilinx PCI core and wrote the
associated Linux driver.

My observations of interrupt latency using
a similar setup to what you describe showed
50usec is common but rare events on
the order of milliseconds are possible.
You are probably correct that the
problem as a poorly behaved driver.

If you have complete control over every system
your device is installed in, you can
find and eliminate any device that
causes high interrupt latency.

If you don't have that control, your hardware
needs to tolerate interrupt latency of
that magnitude.

You describe an implementation with a single
DMA buffer. You could switch to multiple
buffers (ring structure or 2 alternating buffers)
with an interrupt triggered after each
buffer is exhausted (I use a ring of buffers).
The remaining buffers allow the transfer to
continue while waiting for ISR execution.

Or, more crudely, trigger the interrupt when
the single buffer reaches some low water mark
and poll in the ISR for actual completion.

-- 
Paul Fulghum
Microgate Systems, Ltd.
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