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Date:   Thu, 31 Oct 2019 00:36:26 +0100
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Subject: Re: [RFC PATCH 2/3] dt-bindings: net: phy: Add support for AT803X
To:     Florian Fainelli <f.fainelli@gmail.com>,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        netdev@vger.kernel.org
From:   Michael Walle <michael@walle.cc>
Message-ID: <A61073BA-743E-499F-A1D0-BFE40F0ED05A@walle.cc>
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Am 31=2E Oktober 2019 00:28:47 MEZ schrieb Florian Fainelli <f=2Efainelli@g=
mail=2Ecom>:
>On 10/30/19 3:42 PM, Michael Walle wrote:
>> Document the Atheros AR803x PHY bindings=2E
>>=20
>> Signed-off-by: Michael Walle <michael@walle=2Ecc>
>> ---
>>  =2E=2E=2E/bindings/net/atheros,at803x=2Eyaml          | 58
>+++++++++++++++++++
>>  include/dt-bindings/net/atheros-at803x=2Eh      | 13 +++++
>>  2 files changed, 71 insertions(+)
>>  create mode 100644
>Documentation/devicetree/bindings/net/atheros,at803x=2Eyaml
>>  create mode 100644 include/dt-bindings/net/atheros-at803x=2Eh
>>=20
>> diff --git
>a/Documentation/devicetree/bindings/net/atheros,at803x=2Eyaml
>b/Documentation/devicetree/bindings/net/atheros,at803x=2Eyaml
>> new file mode 100644
>> index 000000000000=2E=2E60500fd90fd8
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/net/atheros,at803x=2Eyaml
>> @@ -0,0 +1,58 @@
>> +# SPDX-License-Identifier: GPL-2=2E0+
>> +%YAML 1=2E2
>> +---
>> +$id: http://devicetree=2Eorg/schemas/net/atheros,at803x=2Eyaml#
>> +$schema: http://devicetree=2Eorg/meta-schemas/core=2Eyaml#
>> +
>> +title: Atheros AR803x PHY
>> +
>> +maintainers:
>> +  - TBD
>> +
>> +description: |
>> +  Bindings for Atheros AR803x PHYs
>> +
>> +allOf:
>> +  - $ref: ethernet-phy=2Eyaml#
>> +
>> +properties:
>> +  atheros,clk-out-frequency:
>> +    description: Clock output frequency in Hertz=2E
>> +    enum: [ 25000000, 50000000, 62500000, 125000000 ]
>> +
>> +  atheros,clk-out-strength:
>> +    description: Clock output driver strength=2E
>> +    enum: [ 0, 1, 2 ]
>> +
>> +  atheros,keep-pll-enabled:
>> +    description: |
>> +      If set, keep the PLL enabled even if there is no link=2E Useful
>if you
>> +      want to use the clock output without an ethernet link=2E
>
>This is more of a policy than a hardware description=2E Implementing this
>has a PHY tunable, possibly as a form of auto-power down
>
>> +    type: boolean
>> +
>> +  atheros,rgmii-io-1v8:
>> +    description: |
>> +      The PHY supports RGMII I/O voltages of 2=2E5V, 1=2E8V and 1=2E5V=
=2E By
>default,
>> +      the PHY uses a voltage of 1=2E5V=2E If this is set, the voltage
>will changed
>> +      to 1=2E8V=2E
>
>will be changed?

oh=2E=2E yes of course=2E=20

>This looks like a possibly dangerous configuration as it really can
>lead
>to some good damage happening on the pins if there is an incompatible
>voltage on the MAC and PHY side=2E=2E=2E of course, you have no way to te=
ll
>ahead of time other than by looking at the board schematics, lovely=2E

correct=2E=2E although the standard mode of 1=2E5V has a max high voltage =
of 1=2E8V so this seems to be safe=2E But I guess no one has ever really th=
ough about how to really configure that safely=2E

>Does the PHY come up in some sort of super isolatation mode by default
>at least?

not that I'm aware of=2E also=2E=2E the rgmii mode just works without any =
setup (apart from the delay and voltage settings)=20

-michael=20