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From:   Jason Gunthorpe <jgg@mellanox.com>
To:     Ralph Campbell <rcampbell@nvidia.com>
CC:     Jerome Glisse <jglisse@redhat.com>,
        John Hubbard <jhubbard@nvidia.com>,
        Christoph Hellwig <hch@lst.de>,
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        "linux-mm@kvack.org" <linux-mm@kvack.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 3/3] mm/hmm/test: add self tests for HMM
Thread-Topic: [PATCH v3 3/3] mm/hmm/test: add self tests for HMM
Thread-Index: AQHVidvRl0DiLfVRckS4hHS5dqmJyadx8UKAgAA3LICAACCkgIABo4oAgADQ2QCAAE/3AIAAAcwA
Date:   Thu, 31 Oct 2019 17:34:42 +0000
Message-ID: <20191031173438.GL22766@mellanox.com>
References: <20191023195515.13168-1-rcampbell@nvidia.com>
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On Thu, Oct 31, 2019 at 10:28:12AM -0700, Ralph Campbell wrote:
> > > > > > It seems especially over-complicated to use a full page table l=
ayout
> > > > > > for this, wouldn't something simple like an xarray be good enou=
gh for
> > > > > > test purposes?
> > > > >=20
> > > > > Possibly. A page table is really just a lookup table from virtual=
 address
> > > > > to pfn/page. Part of the rationale was to mimic what a real devic=
e
> > > > > might do.
> > > >=20
> > > > Well, but the details of the page table layout don't see really
> > > > important to this testing, IMHO.
> > >=20
> > > One problem with XArray is that on 32-bit machines the value would
> > > need to be u64 to hold a pfn which won't fit in a ULONG_MAX.
> > > I guess we could make the driver 64-bit only.
> >=20
> > Why would a 32 bit machine need a 64 bit pfn?
> >=20
>=20
> On x86, Physical Address Extension (PAE) uses a 64 bit PTE.
> See arch/x86/include/asm/pgtable_32_types.h which includes
> arch/x86/include/asm/pgtable-3level_types.h.

That is the content of the PTE, not the address of the PTE. In this
case the xarray index is the 'virtual' address of the fictional device
and it can easily be 32 bits with no problem

Jason