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[209.85.128.54]) by smtp.gmail.com with ESMTPSA id i6sm164142eds.96.2019.10.31.19.42.48 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 31 Oct 2019 19:42:49 -0700 (PDT) Received: by mail-wm1-f54.google.com with SMTP id q70so7980418wme.1 for ; Thu, 31 Oct 2019 19:42:48 -0700 (PDT) X-Received: by 2002:a7b:c925:: with SMTP id h5mr7292349wml.61.1572576168752; Thu, 31 Oct 2019 19:42:48 -0700 (PDT) MIME-Version: 1.0 References: <20191031231104.30725-1-karlp@tweak.net.au> In-Reply-To: <20191031231104.30725-1-karlp@tweak.net.au> From: Chen-Yu Tsai Date: Fri, 1 Nov 2019 10:42:37 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 1/3] ARM: dts: sunxi: h3/h5: add missing uart2 rts/cts pins To: Karl Palsson Cc: Maxime Ripard , linux-arm-kernel , linux-kernel Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Nov 1, 2019 at 7:16 AM Karl Palsson wrote: > > uart1 and uart3 had existing pin definitions for the rts/cts pairs. > Add definitions for uart2 as well. > > Signed-off-by: Karl Palsson > --- > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > index 84977d4eb97a..2d8637300321 100644 > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > @@ -472,6 +472,11 @@ > function = "uart2"; > }; > > + uart2_rts_cts_pins: uart2-rts-cts-pins { We started adding "/omit-if-no-ref/" for all pin definitions that aren't selected by default. I think we can do this wholesale for all the ones in this file after this patch is merged though. So, Acked-by: Chen-Yu Tsai > + pins = "PA2", "PA3"; > + function = "uart2"; > + }; > + > uart3_pins: uart3-pins { > pins = "PA13", "PA14"; > function = "uart3"; > -- > 2.20.1 >