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From:   Abel Vesa <abel.vesa@nxp.com>
To:     Peng Fan <peng.fan@nxp.com>
CC:     "sboyd@kernel.org" <sboyd@kernel.org>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
        "festevam@gmail.com" <festevam@gmail.com>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>,
        dl-linux-imx <linux-imx@nxp.com>,
        Anson Huang <anson.huang@nxp.com>,
        Jacky Bai <ping.bai@nxp.com>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Leonard Crestez <leonard.crestez@nxp.com>
Subject: Re: [PATCH] clk: imx: clk-composite-8m: add lock to gate/mux
Thread-Topic: [PATCH] clk: imx: clk-composite-8m: add lock to gate/mux
Thread-Index: AQHVkJ1nitbWRrQWUkuauMi+K6eGNad2IPkA
Date:   Fri, 1 Nov 2019 10:42:49 +0000
Message-ID: <20191101104248.qqpt3hg437rccsri@fsr-ub1664-175>
References: <1572603166-24594-1-git-send-email-peng.fan@nxp.com>
In-Reply-To: <1572603166-24594-1-git-send-email-peng.fan@nxp.com>
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On 19-11-01 10:16:19, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
>=20
> There is a lock to diviver in the composite driver, but that's not
> enought. lock to gate/mux are also needed to provide exclusive access
> to the register.
>=20
> Fixes: d3ff9728134e ("clk: imx: Add imx composite clock")
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Looks good to me.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
>  drivers/clk/imx/clk-composite-8m.c | 2 ++
>  1 file changed, 2 insertions(+)
>=20
> diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-com=
posite-8m.c
> index e0f25983e80f..20f7c91c03d2 100644
> --- a/drivers/clk/imx/clk-composite-8m.c
> +++ b/drivers/clk/imx/clk-composite-8m.c
> @@ -142,6 +142,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const cha=
r *name,
>  	mux->reg =3D reg;
>  	mux->shift =3D PCG_PCS_SHIFT;
>  	mux->mask =3D PCG_PCS_MASK;
> +	mux->lock =3D &imx_ccm_lock;
> =20
>  	div =3D kzalloc(sizeof(*div), GFP_KERNEL);
>  	if (!div)
> @@ -161,6 +162,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const cha=
r *name,
>  	gate_hw =3D &gate->hw;
>  	gate->reg =3D reg;
>  	gate->bit_idx =3D PCG_CGC_SHIFT;
> +	gate->lock =3D &imx_ccm_lock;
> =20
>  	hw =3D clk_hw_register_composite(NULL, name, parent_names, num_parents,
>  			mux_hw, &clk_mux_ops, div_hw,
> --=20
> 2.16.4
>=20