Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Date:   Fri, 01 Nov 2019 15:13:37 +0000
Message-ID: <86eeyry6hq.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Zenghui Yu <yuzenghui@huawei.com>
Cc:     <kvmarm@lists.cs.columbia.edu>, <linux-kernel@vger.kernel.org>,
        Eric Auger <eric.auger@redhat.com>,
        James Morse <james.morse@arm.com>,
        Julien Thierry <julien.thierry.kdev@gmail.com>,
        Suzuki K Poulose <suzuki.poulose@arm.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        "Andrew Murray" <Andrew.Murray@arm.com>,
        Jayachandran C <jnair@marvell.com>,
        "Robert Richter" <rrichter@marvell.com>
Subject: Re: [PATCH v2 09/36] irqchip/gic-v3: Add GICv4.1 VPEID size discovery
In-Reply-To: <ec979d9b-cfe8-bfd8-fc4c-c41a602b2494@huawei.com>
References: <20191027144234.8395-1-maz@kernel.org>
        <20191027144234.8395-10-maz@kernel.org>
        <ec979d9b-cfe8-bfd8-fc4c-c41a602b2494@huawei.com>
User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue)
 FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26
 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO)
MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue")
Content-Type: text/plain; charset=US-ASCII
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On Thu, 31 Oct 2019 12:02:24 +0000,
Zenghui Yu <yuzenghui@huawei.com> wrote:
> 
> Hi Marc,
> 
> On 2019/10/27 22:42, Marc Zyngier wrote:
> > While GICv4.0 mandates 16 bit worth of VPEIDs, GICv4.1 allows smaller
> > implementations to be built. Add the required glue to dynamically
> > compute the limit.
> > 
> > Signed-off-by: Marc Zyngier <maz@kernel.org>
> > ---
> >   drivers/irqchip/irq-gic-v3-its.c   | 11 ++++++++++-
> >   drivers/irqchip/irq-gic-v3.c       |  3 +++
> >   include/linux/irqchip/arm-gic-v3.h |  5 +++++
> >   3 files changed, 18 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> > index 94c9c2e9f917..40912b3fb0e1 100644
> > --- a/drivers/irqchip/irq-gic-v3-its.c
> > +++ b/drivers/irqchip/irq-gic-v3-its.c
> > @@ -121,7 +121,16 @@ struct its_node {
> >   #define ITS_ITT_ALIGN		SZ_256
> >     /* The maximum number of VPEID bits supported by VLPI commands
> > */
> > -#define ITS_MAX_VPEID_BITS	(16)
> > +#define ITS_MAX_VPEID_BITS						\
> > +	({								\
> > +		int nvpeid = 16;					\
> > +		if (gic_rdists->has_rvpeid &&				\
> > +		    gic_rdists->gicd_typer2 & GICD_TYPER2_VIL)		\
> > +			nvpeid = 1 + (gic_rdists->gicd_typer2 &		\
> > +				      GICD_TYPER2_VID);			\
> 
> Does it make sense to let nvpeid not more than 16 here? As the spec says
> "Values above 0x0F are RESERVED". But I don't know why should we have
> this restriction ;-)

This is something that Andrew raised in the previous version. My take
on this is that properly implemented HW should give us something that
matches the spec (in the 0-15 range), and I don't think that guarding
against that is useful at this stage.

My understanding is that once the architecture allows using the 16-31
range, we'll either use it directly because it is just a natural
extension to the existing range, or they mean something different
altogether and we'll get a new discovery bit somewhere.

> Either way,
> 
> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>

Thanks,

	M.

-- 
Jazz is not dead, it just smells funny.