Received: by 2002:a25:31c3:0:0:0:0:0 with SMTP id x186csp3150146ybx; Sun, 3 Nov 2019 11:54:43 -0800 (PST) X-Google-Smtp-Source: APXvYqwkOnM3/hnhxTj6QFfliA3/m+yYOrgohYa7p89FQuRi9gdSdENSS/mkitZJat3Ff/h8pl3C X-Received: by 2002:a05:6402:105a:: with SMTP id e26mr24811989edu.229.1572810882961; Sun, 03 Nov 2019 11:54:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572810882; cv=none; d=google.com; s=arc-20160816; b=JzQYcxyMZhwYn2I+gHSPxsofWUehisve2ZVrGZmH+gRyeh0ASWEZaed4WK31WFdH5W JzcixYKvqBW8Iai2O9zGSVtxGfLcK8ZK7S7wLAlW5/LFkdFwiHnCKrNMGYJNScoRtYHw HYqNf3b6qeVrBwcP4I+IG0FYuiah7nHrv5BCXbWlQbp7F9OZkkycZrdTgTDYlFDOt1lX JoSYAJ5mBTwta6U7XjAXmVUtIN3khNXQP/5sN7T6i4Mlj5wah82t4XuQXiC/lQLP0vFi rYcU6qCHcLIQVV1YwNIUF2s8YnyO9+fHurHPPpAbY5eUfWtZF5AAlTop7ghtMnfA5UfG INVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject; bh=rTG1L9aHJoAtL42CYzuRVvyOXz7jlR1h5ExQz/00LXg=; b=LJzcklp6qVj+zhOuBeibXn6mItcM/lGN5Kq8P3ERWE4RDEdycQRgW4ZolfnSpF9pjr HhiXZcCSPRIV5NDcWA1n5iuIeOYypzX9gbsKLcpzESNTFt+kSFJd8ZG+Jcwxq8ucexA6 XsE9t/w9rNMmrbWx5QS+oGN1WXoB0l2W7DYQZAN8xmq7GoxGDUBUOdRrH8Ym9ULWZG5E CLq8eKNVtV7wVMnn0GpxsMG4uUeTiopxnsCXbgmWrtCJwuisK3gOVlSkbdn1nCwHlIgt 6UP6PT7V7nUSvtweE9iB454CBqEWp+ISHg4HTxmSvdhPT9/3GjphSfX0y4A1uSopyXQr tFZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=hz45cfuI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id lu22si10192592ejb.127.2019.11.03.11.54.18; Sun, 03 Nov 2019 11:54:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=hz45cfuI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728160AbfKCTxp (ORCPT + 99 others); Sun, 3 Nov 2019 14:53:45 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:9104 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727343AbfKCTxo (ORCPT ); Sun, 3 Nov 2019 14:53:44 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 03 Nov 2019 11:53:45 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 03 Nov 2019 11:53:38 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 03 Nov 2019 11:53:38 -0800 Received: from [10.110.48.28] (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 3 Nov 2019 19:53:37 +0000 Subject: Re: [PATCH 19/19] Documentation/vm: add pin_user_pages.rst To: Andrew Morton CC: Al Viro , Alex Williamson , Benjamin Herrenschmidt , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Christoph Hellwig , Dan Williams , Daniel Vetter , Dave Chinner , David Airlie , "David S . Miller" , Ira Weiny , Jan Kara , Jason Gunthorpe , Jens Axboe , Jonathan Corbet , =?UTF-8?B?SsOpcsO0bWUgR2xpc3Nl?= , Magnus Karlsson , Mauro Carvalho Chehab , Michael Ellerman , Michal Hocko , Mike Kravetz , Paul Mackerras , Shuah Khan , Vlastimil Babka , , , , , , , , , , , , , LKML References: <20191030224930.3990755-1-jhubbard@nvidia.com> <20191030224930.3990755-20-jhubbard@nvidia.com> X-Nvconfidentiality: public From: John Hubbard Message-ID: <58d3ef87-85ef-a69d-5cf7-1719ff356048@nvidia.com> Date: Sun, 3 Nov 2019 11:53:37 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20191030224930.3990755-20-jhubbard@nvidia.com> X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1572810825; bh=rTG1L9aHJoAtL42CYzuRVvyOXz7jlR1h5ExQz/00LXg=; h=X-PGP-Universal:Subject:To:CC:References:X-Nvconfidentiality:From: Message-ID:Date:User-Agent:MIME-Version:In-Reply-To: X-Originating-IP:X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=hz45cfuI6ZB24IXq0tlVG+4gOOw0rO1aR3a1v+mNE3URSP536c/QI/nw4iVi4Q3Fg ZvhfjRg3c8U4Zeed5IN0S8La0/yhKPqXLcaka8zujsYCnTFzskkYWmX6ZMKm85uc53 903Xo+ojBBu648JazllTkreHad3wmqcM3sQfIPNK3XPWIubatS+4uPpiaSake+maws O3mb+7lTk0b/qWmINewSdXIPlnBwUrlkcxoUQTGi1jJWPWnSrL74fzVKeEWjMvAjbH 5wXYgJG8qyFZYCSM/zx8jBY5FMvGDHZIQbt9J9oHql6kjp+O+lMMcuF1F8/mAcyFV4 Yo4Vz3wx3lQSQ== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/30/19 3:49 PM, John Hubbard wrote: ... > +* struct page may not be increased in size for this, and all fields are already > + used. > + > +* Given the above, we can overload the page->_refcount field by using, sort of, > + the upper bits in that field for a dma-pinned count. "Sort of", means that, > + rather than dividing page->_refcount into bit fields, we simple add a medium- > + large value (GUP_PIN_COUNTING_BIAS, initially chosen to be 1024: 10 bits) to > + page->_refcount. This provides fuzzy behavior: if a page has get_page() called > + on it 1024 times, then it will appear to have a single dma-pinned count. > + And again, that's acceptable. > + > +This also leads to limitations: there are only 32-10==22 bits available for a > +counter that increments 10 bits at a time. > + The above claim is just a "bit" too optimistic, by one bit: page->_refcount, being an atomic_t which uses a signed int (and we use the sign bit to check for overflow), only has 31 total bits available for actual counting, not 32. I'll adjust the documentation in v2, to account for this. thanks, John Hubbard NVIDIA