Received: by 2002:a25:31c3:0:0:0:0:0 with SMTP id x186csp3703395ybx; Mon, 4 Nov 2019 01:21:09 -0800 (PST) X-Google-Smtp-Source: APXvYqwcloW2VXQmlaNg9LG6kDBc+EvODURNdmli9rNQfS7Wkr69t1oZRbKcuDajhrM457m7nOt1 X-Received: by 2002:a50:b626:: with SMTP id b35mr24079821ede.183.1572859269584; Mon, 04 Nov 2019 01:21:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572859269; cv=none; d=google.com; s=arc-20160816; b=x/qpycB8Z03H8by5fZzTN5pEpzpBEXvZ8VCEEBw2q7n81lQos+8Jn7qKJwEw8XZQ51 kEzIoEFFM/8Cu6ILgm+UtsTKpzPrKI5b9ODnn/wmsB+x4thFZxLkfWUqQEe2MAIPqcAQ Ebsgbi2wvfoIERanQsEcb47Z5AdOJQC1OON2+p0c3+9lADSDhxH2VZp6gy961wHkH2fu LCyeQOrJEEjDG0dXno0fUMn+5XxozHB339+KHB2x63POhRTyMOlrhQ3lX7QHntH3/REV aBsuGYHwl9eo5X8v3JuBBzfx/wbbUi0ahbn5fOmrpDzluWeCMFaE/R4Vh7zcRDvZKuOu MsvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:date:message-id:cc:to:subject:from; bh=ZydDl4B+GYZAjIdyfgS0RYhPCErXOBMCWUxX1j83oOQ=; b=1GNoW3HGGCNEPcDjF9A+HssSbWNCx9IDgE+4mRHLzwD43HZ9prJM0VYJbuUowqPvJ+ fiT8C6apa+hcGiXZMJ/yFYs4/PphcEqYNB2TA42xteF7QDVSIs4I2l9jNO0Bs4URaNQN 7wY4gUTb1e1bkHwkDOCzF6E3EINsXAL/1W8MMRwTKGj5+N11P8kaYz02i41IiURmD3Ue g4+3yb8Udtspqj0W9oQvsb4cASC6OloV/nSDSNjr6gh3C6sMpOOuV5neiq+I4ARLLpHt yjZk6LgViEE7VPP6pX/ZbQh2ZmRYat6cHZ24LFCCigOp7R8XiORYkUXA7K8xUzEl9cLo bipA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q15si1383358ejm.31.2019.11.04.01.20.45; Mon, 04 Nov 2019 01:21:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728255AbfKDJSN (ORCPT + 99 others); Mon, 4 Nov 2019 04:18:13 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:5698 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727138AbfKDJSM (ORCPT ); Mon, 4 Nov 2019 04:18:12 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id E9CEA40EDF38CDC4749A; Mon, 4 Nov 2019 17:18:09 +0800 (CST) Received: from [127.0.0.1] (10.74.221.148) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Mon, 4 Nov 2019 17:18:00 +0800 From: Shaokun Zhang Subject: [RFC] About perf-mem command support on arm64 platform To: , CC: Jiri Olsa , Arnaldo Carvalho de Melo , Mark Rutland , Will Deacon , , , , Jonathan Cameron Message-ID: <74f8ddb5-13cc-5dce-82a6-ca8bd02f8175@hisilicon.com> Date: Mon, 4 Nov 2019 17:18:00 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.74.221.148] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi all, perf-mem is used to profile memory access which has been implemented on x86 platform. It needs mem-stores events and mem-loads/load-latency. For mem-stores events, it is MEM_INST_RETIRED_ALL_STORES whose raw number is r82d0, and mem-loads/load-latency is from PEBS if I follow its code. Now, for some arm64 cores, like HiSilicon's tsv110 and ARM's Neoverse N1, has supported the SPE(Statistical Profiling Extensions), so is it a possibility that perf-mem is supported on arm64? https://developer.arm.com/ip-products/processors/neoverse/neoverse-n1 For arm64 PMU, it has 'st_retired' event that the event number is 0x0007 which is equal to mem-stores on x86, if we want support perf-mem, it seems that 'st_retired' shall be replaced by 'mem-stores' in arch/arm64/kernel/perf_event.c file. Of course, the cpu core should support st_retired event. I'm not sure Will/Mark are happy on this.;-) For mem-loads/load-latency, we can derive them from SPE sampled data which supports by load_filter and min_latency in SPE driver. and we may do some work on tools/perf/builtin-mem.c. From the above conditions, it seems that we may have the opportunity to support the perf-mem command on arm64. I'm not very sure about it, so I send this RFC and any comments are welcome. Thanks, Shaokun