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[209.132.180.67]) by mx.google.com with ESMTP id i33si7558274edc.279.2019.11.04.05.12.51; Mon, 04 Nov 2019 05:13:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728956AbfKDNMC (ORCPT + 99 others); Mon, 4 Nov 2019 08:12:02 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:37378 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727236AbfKDNMB (ORCPT ); Mon, 4 Nov 2019 08:12:01 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 8F5C42910DE0A13ECD44; Mon, 4 Nov 2019 21:11:59 +0800 (CST) Received: from [127.0.0.1] (10.177.223.23) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Mon, 4 Nov 2019 21:11:49 +0800 Subject: Re: stable-rc-4.19: cpufeature.c:909:21: error: 'MIDR_HISI_TSV110' undeclared To: Greg Kroah-Hartman CC: Naresh Kamboju , Sasha Levin , Mark Rutland , , , , open list , linux- stable , , , , , Dave P Martin , References: <98f10e13-8ec8-1690-a867-f212bcea969f@huawei.com> <20191104105910.GB1945210@kroah.com> From: Hanjun Guo Message-ID: Date: Mon, 4 Nov 2019 21:11:12 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <20191104105910.GB1945210@kroah.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.223.23] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2019/11/4 18:59, Greg Kroah-Hartman wrote: > On Mon, Nov 04, 2019 at 09:10:06AM +0800, Hanjun Guo wrote: >> Hi Sasha, Greg, >> >> On 2019/11/4 7:22, Naresh Kamboju wrote: >>> stable rc 4.19 branch build broken for arm64 with the below error log, >>> >>> Build error log, >>> arch/arm64/kernel/cpufeature.c: In function 'unmap_kernel_at_el0': >>> arch/arm64/kernel/cpufeature.c:909:21: error: 'MIDR_HISI_TSV110' >>> undeclared (first use in this function); did you mean >>> 'GICR_ISACTIVER0'? >>> MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), >>> ^ >>> arch/arm64/include/asm/cputype.h:141:12: note: in definition of macro >>> 'MIDR_RANGE' >>> .model = m, \ >>> ^ >>> arch/arm64/kernel/cpufeature.c:909:3: note: in expansion of macro >>> 'MIDR_ALL_VERSIONS' >>> MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), >>> ^~~~~~~~~~~~~~~~~ >>> arch/arm64/kernel/cpufeature.c:909:21: note: each undeclared >>> identifier is reported only once for each function it appears in >>> MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), >>> ^ >>> arch/arm64/include/asm/cputype.h:141:12: note: in definition of macro >>> 'MIDR_RANGE' >>> .model = m, \ >>> ^ >>> arch/arm64/kernel/cpufeature.c:909:3: note: in expansion of macro >>> 'MIDR_ALL_VERSIONS' >>> MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), >> >> Patch "efd00c7 arm64: Add MIDR encoding for HiSilicon Taishan CPUs" needs to >> be bacported as well, would you like me to do that, or just cherry-pick by yourself? > > I need the backport please, cherry-pick fails :( I will send it out later. Thanks Hanjun