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[209.132.180.67]) by mx.google.com with ESMTP id a60si8849815edf.169.2019.11.04.14.32.18; Mon, 04 Nov 2019 14:32:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@googlemail.com header.s=20161025 header.b=a+MdlyvE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=googlemail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729709AbfKDWbp (ORCPT + 99 others); Mon, 4 Nov 2019 17:31:45 -0500 Received: from mail-oi1-f196.google.com ([209.85.167.196]:43186 "EHLO mail-oi1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729122AbfKDWbo (ORCPT ); Mon, 4 Nov 2019 17:31:44 -0500 Received: by mail-oi1-f196.google.com with SMTP id l20so3610890oie.10; Mon, 04 Nov 2019 14:31:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=/geFBMEqf7twdLKHSVdVT6FyWVKwx2NVIgtA+twsQkE=; b=a+MdlyvEiOU8aVaiBQk7eZ1yzA7XLzs5bUKhswBKAOj829P1WsrId1fjxcmSMHq8gj NspcXXwicor7YnC+bnT8Xxk+tmbIiLz10bUdTlShG1kpID8r4HDiZQGeEbDUGE6LwMaU dj9FsHVklDGCuQGMM3cJWuIeRBzXzY1LdoKQk6RtWq6FAoGwHuCDXcXU083BhStrehgo 44ejbg2Ezjdd82Ei9VCASuj382uI5TGCAnogkliUyv97kHZWOfQcNHDgXk8w4uGUQFi+ 10StfI7b/HKvJ2jmqQjin2gdn4ehUBykG4EMkTjlhV+U9jrXVqeKQoCUsKuuXQXDcRIK ZTpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=/geFBMEqf7twdLKHSVdVT6FyWVKwx2NVIgtA+twsQkE=; b=StVs7HG1dMoc8IM3MZ5tPLR6GX2mSOSCawAszsLN6X4zorBpQZEU6FTqOSZGD7i512 7q7x7UppOZkoctR3yMvE68vVM3BQp7FN4SgR2uxa2Ii9Xq3+JtsiV5HTiQN+0aHiFnSX y4lceymmce4o6M3kfDXBRXoYQIoCVVIm0EG/mBKuJOfT/T7MbGyYYaAieMFzg8UCfiIq sHrDVWIG2Rllr98xV7ddEuAk15B8eBzZ+pNjjQv75pjWUMsUo3+Wlm0evtaT5/GHWfpw Z9Enn0O9pH1G5UMR8fmXkGwd70S1V8TogKSyGFEZhIKnXOAd9u0CRSc+zbLMPmE2SyjY UTpw== X-Gm-Message-State: APjAAAUF+YWc0f0hujR6oy3wX56WyoHHN2UaVcRSAw/jSkwh356xbFqZ c7bXqdERDCG52s9Rc90uYEjN1d+HUqEEWt5ZwQ4= X-Received: by 2002:aca:504d:: with SMTP id e74mr1229364oib.140.1572906703760; Mon, 04 Nov 2019 14:31:43 -0800 (PST) MIME-Version: 1.0 References: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com> <20191027161805.1176321-4-martin.blumenstingl@googlemail.com> <1jd0e83vyp.fsf@starbuckisacylon.baylibre.com> In-Reply-To: <1jd0e83vyp.fsf@starbuckisacylon.baylibre.com> From: Martin Blumenstingl Date: Mon, 4 Nov 2019 23:31:32 +0100 Message-ID: Subject: Re: [PATCH v2 3/5] clk: meson: meson8b: change references to the XTAL clock to use the name To: Jerome Brunet Cc: Neil Armstrong , linux-amlogic@lists.infradead.org, khilman@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jerome, On Mon, Nov 4, 2019 at 9:08 AM Jerome Brunet wrote: > > > On Sun 27 Oct 2019 at 17:18, Martin Blumenstingl wrote: > > > The XTAL clock is an actual crystal which is mounted on the PCB. Thus > > the meson8b clock controller driver should not provide the XTAL clock. > > > > The meson8b clock controller driver must not use references to > > the meson8b_xtal clock anymore before we can provide the XTAL clock > > via OF. Replace the references to the meson8b_xtal.hw by using > > clk_parent_data.name = "xtal" (along with index = -1) because this works > > regardless how the XTAL clock is registered (either as fixed-clock in > > the .dtb or - if missing - when registered in the meson8b clock > > controller driver). > > > > Signed-off-by: Martin Blumenstingl > > --- > > drivers/clk/meson/meson8b.c | 73 ++++++++++++++++++++----------------- > > 1 file changed, 39 insertions(+), 34 deletions(-) > > > > diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c > > index d376f80e806d..b785b67baf2b 100644 > > --- a/drivers/clk/meson/meson8b.c > > +++ b/drivers/clk/meson/meson8b.c > > @@ -97,8 +97,9 @@ static struct clk_regmap meson8b_fixed_pll_dco = { > > .hw.init = &(struct clk_init_data){ > > .name = "fixed_pll_dco", > > .ops = &meson_clk_pll_ro_ops, > > - .parent_hws = (const struct clk_hw *[]) { > > - &meson8b_xtal.hw > > + .parent_data = &(const struct clk_parent_data) { > > + .name = "xtal", > > + .index = -1, > > if I got correctly, when transitioning to DT, you can specify both > "fw_name" and "name". CCF should try to get the clock through DT and > fallback to global name matching if not available thank you for the hint - I may even get away with just setting fw_name if I understand clk_core_get() correctly. I'll try that during the weekend and report back Martin