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[209.132.180.67]) by mx.google.com with ESMTP id cw1si12857304ejb.117.2019.11.05.00.04.07; Tue, 05 Nov 2019 00:04:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388054AbfKEIAo convert rfc822-to-8bit (ORCPT + 99 others); Tue, 5 Nov 2019 03:00:44 -0500 Received: from rtits2.realtek.com ([211.75.126.72]:34205 "EHLO rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387810AbfKEIAo (ORCPT ); Tue, 5 Nov 2019 03:00:44 -0500 Authenticated-By: X-SpamFilter-By: BOX Solutions SpamTrap 5.62 with qID xA580QQg008052, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (RTITCASV01.realtek.com.tw[172.21.6.18]) by rtits2.realtek.com.tw (8.15.2/2.57/5.78) with ESMTPS id xA580QQg008052 (version=TLSv1 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 5 Nov 2019 16:00:26 +0800 Received: from RTITMBSVM04.realtek.com.tw ([fe80::e404:880:2ef1:1aa1]) by RTITCASV01.realtek.com.tw ([::1]) with mapi id 14.03.0468.000; Tue, 5 Nov 2019 16:00:25 +0800 From: James Tai To: "linux-realtek-soc@lists.infradead.org" CC: "linux-arm-kernel@lists.infradead.org" , "'linux-kernel@vger.kernel.org'" , Mark Rutland , "Rob Herring" , =?iso-8859-1?Q?Andreas_F=E4rber?= Subject: [PATCH] arm64: dts: realtek: Add Realtek rtd1619 and mjolnir Thread-Topic: [PATCH] arm64: dts: realtek: Add Realtek rtd1619 and mjolnir Thread-Index: AdWTrwRiu8TDC5guRneVMItRk6mPLw== Date: Tue, 5 Nov 2019 08:00:25 +0000 Message-ID: <43B123F21A8CFE44A9641C099E4196FFCF91BEFA@RTITMBSVM04.realtek.com.tw> Accept-Language: zh-TW, en-US Content-Language: zh-TW X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.21.190.187] Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds a generic devicetree board file and a dtsi for Realtek rtd1619 SoC. Signed-off-by: james tai --- arch/arm64/boot/dts/realtek/Makefile | 3 + .../boot/dts/realtek/rtd1619-mjolnir.dts | 31 +++++++ arch/arm64/boot/dts/realtek/rtd1619.dtsi | 91 +++++++++++++++++++ arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 66 ++++++++++++++ 4 files changed, 191 insertions(+) create mode 100644 arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1619.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd16xx.dtsi diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile index 555638ada721..a58353a1d99a 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -7,3 +7,6 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb + +dtb-$(CONFIG_ARCH_REALTEK) += rtd1619-mjolnir.dtb + diff --git a/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts b/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts new file mode 100644 index 000000000000..def5964c7715 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1619.dtsi" + +/ { + compatible = "realtek,rtd1619"; + model= "Realtek Mjolnir EVB"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; +}; + +&uart0 { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/realtek/rtd1619.dtsi b/arch/arm64/boot/dts/realtek/rtd1619.dtsi new file mode 100644 index 000000000000..ac5c737b04db --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1619.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1619 SoC + * + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +#include "rtd16xx.dtsi" + +/ { + compatible = "realtek,rtd1619"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x000>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x400>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x500>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + l2: l2-cache { + compatible = "cache"; + next-level-cache = <&l3>; + + }; + + l3: l3-cache { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; + +&arm_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, + <&cpu3>, <&cpu4>, <&cpu5>; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi new file mode 100644 index 000000000000..ef56c6ed6663 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1619 SoC + * + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +#include +#include + +/{ + compatible = "realtek,rtd1619"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + arm_pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + osc27M: osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "osc27M"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial0@98007800 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x98007800 0x0 0x400>, + <0x0 0x98007000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <0 68 4>; + clock-frequency = <27000000>; + status = "disabled"; + }; + + gic: interrupt-controller@ff100000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + redistributor-stride = <0x0 0x20000>; + #redistributor-regions = <1>; + reg = <0x0 0xff100000 0x0 0x10000>, + <0x0 0xff140000 0x0 0x200000>; + interrupts = ; + }; + }; +}; -- 2.17.1