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From:   Ganapatrao Prabhakerrao Kulkarni <gkulkarni@marvell.com>
To:     "linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
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CC:     "peterz@infradead.org" <peterz@infradead.org>,
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        "will@kernel.org" <will@kernel.org>,
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        "corbet@lwn.net" <corbet@lwn.net>,
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Subject: [PATCH 1/2] perf/core: Adding capability to disable PMUs event
 multiplexing
Thread-Topic: [PATCH 1/2] perf/core: Adding capability to disable PMUs event
 multiplexing
Thread-Index: AQHVlD2/iZKAhmDmiEmnYqFl7ZfEnQ==
Date:   Wed, 6 Nov 2019 01:01:40 +0000
Message-ID: <1573002091-9744-2-git-send-email-gkulkarni@marvell.com>
References: <1573002091-9744-1-git-send-email-gkulkarni@marvell.com>
In-Reply-To: <1573002091-9744-1-git-send-email-gkulkarni@marvell.com>
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When PMUs are registered, perf core enables event multiplexing
support by default. There is no provision for PMUs to disable
event multiplexing, if PMUs want to disable due to unavoidable
circumstances like hardware errata etc.

Adding PMU capability flag PERF_PMU_CAP_NO_MUX_EVENTS and support
to allow PMUs to explicitly disable event multiplexing.

Signed-off-by: Ganapatrao Prabhakerrao Kulkarni <gkulkarni@marvell.com>
---
 include/linux/perf_event.h | 1 +
 kernel/events/core.c       | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 61448c19a132..9e18d841daf7 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -247,6 +247,7 @@ struct perf_event;
 #define PERF_PMU_CAP_HETEROGENEOUS_CPUS		0x40
 #define PERF_PMU_CAP_NO_EXCLUDE			0x80
 #define PERF_PMU_CAP_AUX_OUTPUT			0x100
+#define PERF_PMU_CAP_NO_MUX_EVENTS		0x200
=20
 /**
  * struct pmu - generic performance monitoring unit
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 4655adbbae10..65452784f81c 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -1092,6 +1092,10 @@ static void __perf_mux_hrtimer_init(struct perf_cpu_=
context *cpuctx, int cpu)
 	if (pmu->task_ctx_nr =3D=3D perf_sw_context)
 		return;
=20
+	/* No PMU support */
+	if (pmu->capabilities & PERF_PMU_CAP_NO_MUX_EVENTS)
+		return 0;
+
 	/*
 	 * check default is sane, if not set then force to
 	 * default interval (1/tick)
@@ -1117,6 +1121,10 @@ static int perf_mux_hrtimer_restart(struct perf_cpu_=
context *cpuctx)
 	if (pmu->task_ctx_nr =3D=3D perf_sw_context)
 		return 0;
=20
+	/* No PMU support */
+	if (pmu->capabilities & PERF_PMU_CAP_NO_MUX_EVENTS)
+		return 0;
+
 	raw_spin_lock_irqsave(&cpuctx->hrtimer_lock, flags);
 	if (!cpuctx->hrtimer_active) {
 		cpuctx->hrtimer_active =3D 1;
--=20
2.17.1