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Date:   Thu, 7 Nov 2019 09:45:55 +1100
From:   Stephen Rothwell <sfr@canb.auug.org.au>
To:     Bjorn Helgaas <bhelgaas@google.com>,
        Olof Johansson <olof@lixom.net>, Arnd Bergmann <arnd@arndb.de>,
        ARM <linux-arm-kernel@lists.infradead.org>
Cc:     Linux Next Mailing List <linux-next@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Xiaowei Bao <xiaowei.bao@nxp.com>,
        Hou Zhiqiang <Zhiqiang.Hou@nxp.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Fabio Estevam <festevam@gmail.com>,
        Shawn Guo <shawnguo@kernel.org>
Subject: linux-next: manual merge of the pci tree with the arm-soc tree
Message-ID: <20191107094555.6296b943@canb.auug.org.au>
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Hi all,

Today's linux-next merge of the pci tree got a conflict in:

  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

between commit:

  68e36a429ef5 ("arm64: dts: ls1028a: Move thermal-zone out of SoC")

from the arm-soc tree and commit:

  8d49ebe713ab ("arm64: dts: ls1028a: Add PCIe controller DT nodes")

from the pci tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

--=20
Cheers,
Stephen Rothwell

diff --cc arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 8e8a77eb596a,71d7c6949b9e..000000000000
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@@ -611,6 -594,89 +611,58 @@@
  			#thermal-sensor-cells =3D <1>;
  		};
 =20
 -		thermal-zones {
 -			core-cluster {
 -				polling-delay-passive =3D <1000>;
 -				polling-delay =3D <5000>;
 -				thermal-sensors =3D <&tmu 0>;
 -
 -				trips {
 -					core_cluster_alert: core-cluster-alert {
 -						temperature =3D <85000>;
 -						hysteresis =3D <2000>;
 -						type =3D "passive";
 -					};
 -
 -					core_cluster_crit: core-cluster-crit {
 -						temperature =3D <95000>;
 -						hysteresis =3D <2000>;
 -						type =3D "critical";
 -					};
 -				};
 -
 -				cooling-maps {
 -					map0 {
 -						trip =3D <&core_cluster_alert>;
 -						cooling-device =3D
 -							<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 -							<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 -					};
 -				};
 -			};
 -		};
 -
+ 		pcie@3400000 {
+ 			compatible =3D "fsl,ls1028a-pcie";
+ 			reg =3D <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+ 			       0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ 			reg-names =3D "regs", "config";
+ 			interrupts =3D <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ 				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+ 			interrupt-names =3D "pme", "aer";
+ 			#address-cells =3D <3>;
+ 			#size-cells =3D <2>;
+ 			device_type =3D "pci";
+ 			dma-coherent;
+ 			num-viewport =3D <8>;
+ 			bus-range =3D <0x0 0xff>;
+ 			ranges =3D <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000  =
 /* downstream I/O */
+ 				  0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-p=
refetchable memory */
+ 			msi-parent =3D <&its>;
+ 			#interrupt-cells =3D <1>;
+ 			interrupt-map-mask =3D <0 0 0 7>;
+ 			interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH=
>,
+ 					<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ 					<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ 					<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ 			status =3D "disabled";
+ 		};
+=20
+ 		pcie@3500000 {
+ 			compatible =3D "fsl,ls1028a-pcie";
+ 			reg =3D <0x00 0x03500000 0x0 0x00100000   /* controller registers */
+ 			       0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ 			reg-names =3D "regs", "config";
+ 			interrupts =3D <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ 			interrupt-names =3D "pme", "aer";
+ 			#address-cells =3D <3>;
+ 			#size-cells =3D <2>;
+ 			device_type =3D "pci";
+ 			dma-coherent;
+ 			num-viewport =3D <8>;
+ 			bus-range =3D <0x0 0xff>;
+ 			ranges =3D <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000  =
 /* downstream I/O */
+ 				  0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-p=
refetchable memory */
+ 			msi-parent =3D <&its>;
+ 			#interrupt-cells =3D <1>;
+ 			interrupt-map-mask =3D <0 0 0 7>;
+ 			interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH=
>,
+ 					<0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ 					<0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ 					<0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ 			status =3D "disabled";
+ 		};
+=20
  		pcie@1f0000000 { /* Integrated Endpoint Root Complex */
  			compatible =3D "pci-host-ecam-generic";
  			reg =3D <0x01 0xf0000000 0x0 0x100000>;

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