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Thu, 07 Nov 2019 01:01:54 -0800 Received: from [172.19.2.91] (helo=xsjjollys50.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iSdfo-00016I-TX; Thu, 07 Nov 2019 01:01:48 -0800 From: Rajan Vaja To: mturquette@baylibre.com, sboyd@kernel.org, michal.simek@xilinx.com, m.tretter@pengutronix.de, jollys@xilinx.com Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rajan Vaja , Jolly Shah Subject: [PATCH] clk: zynqmp: Correct bit index for divider flag Date: Thu, 7 Nov 2019 01:01:30 -0800 Message-Id: <1573117290-7990-1-git-send-email-rajan.vaja@xilinx.com> X-Mailer: git-send-email 2.7.4 X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(396003)(346002)(39850400004)(136003)(376002)(199004)(189003)(2906002)(106002)(50226002)(51416003)(336012)(7696005)(6666004)(48376002)(356004)(36756003)(107886003)(4326008)(54906003)(16586007)(316002)(36386004)(6636002)(47776003)(478600001)(8676002)(70206006)(186003)(70586007)(4744005)(9786002)(5660300002)(26005)(44832011)(426003)(14444005)(305945005)(2616005)(50466002)(81156014)(81166006)(8936002)(476003)(486006)(126002);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR02MB4512;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;A:1;MX:1; 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Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Signed-off-by: Michal Simek --- drivers/clk/zynqmp/divider.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index d8f5b70d..9e60834 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -2,7 +2,7 @@ /* * Zynq UltraScale+ MPSoC Divider support * - * Copyright (C) 2016-2018 Xilinx + * Copyright (C) 2016-2019 Xilinx * * Adjustable divider clock implementation */ @@ -25,7 +25,7 @@ #define to_zynqmp_clk_divider(_hw) \ container_of(_hw, struct zynqmp_clk_divider, hw) -#define CLK_FRAC BIT(13) /* has a fractional parent */ +#define CLK_FRAC BIT(8) /* has a fractional parent */ /** * struct zynqmp_clk_divider - adjustable divider clock -- 2.7.4