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Thu, 07 Nov 2019 01:44:54 -0800 Received: from xsj-pvapsmtp01 (xsj-smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id xA79iox9004141; Thu, 7 Nov 2019 01:44:51 -0800 Received: from [172.19.2.91] (helo=xsjjollys50.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iSeLS-00005Y-Oq; Thu, 07 Nov 2019 01:44:50 -0800 From: Rajan Vaja To: robh+dt@kernel.org, mark.rutland@arm.com, michal.simek@xilinx.com, harini.katakam@xilinx.com, jan.kiszka@siemens.com, ulf.hansson@linaro.org, xuwei5@hisilicon.com, mripard@kernel.org, heiko@sntech.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rajan Vaja Subject: [PATCH 2/3] arm64: dts: xilinx: Remove dtsi for fixed clock Date: Thu, 7 Nov 2019 01:44:15 -0800 Message-Id: <1573119856-13548-3-git-send-email-rajan.vaja@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573119856-13548-1-git-send-email-rajan.vaja@xilinx.com> References: <1573119856-13548-1-git-send-email-rajan.vaja@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(39860400002)(376002)(396003)(136003)(346002)(199004)(189003)(51416003)(7696005)(6666004)(305945005)(7416002)(76176011)(107886003)(14444005)(356004)(446003)(70586007)(70206006)(4326008)(5660300002)(36386004)(50466002)(16586007)(36756003)(81156014)(8676002)(2906002)(50226002)(81166006)(9786002)(106002)(486006)(126002)(336012)(2616005)(476003)(44832011)(11346002)(186003)(48376002)(478600001)(47776003)(26005)(316002)(426003)(8936002);DIR:OUT;SFP:1101;SCL:1;SRVR:BL0PR02MB6467;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;A:1;MX:1; MIME-Version: 1.0 Content-Type: text/plain X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d6a85ec6-43c7-4a7e-94b1-08d7636727ff X-MS-TrafficTypeDiagnostic: BL0PR02MB6467: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:1468; X-Forefront-PRVS: 0214EB3F68 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qDFT1bs6pKz1MSgHjnKn928v1hyrZUa+izHVctNPxs6ilJphH4x6yDw25q11Q8b3RUrMCDd06fZGjRMaYBw7CO5eET3SwNyEkfukvHkdD+61claarbsNWsNY7W99U3ZPlfPV0i4Q2Rw4qq+ILX/Ag6H/ub3QtaZwGMSHv/oHlAVD246v/KiGL8X11xwvRAgWZzYt2QMJE6kq7HsD2VqSOIXIHx9gxI4QQa5xtILtvjm5YbzEeoNTNUhwqw7BxRGdOxs4vvD25jIYrOIHR9vql0pENbbAAlwh8hXfEa4OZ7yk+JLLsPN88uASrcZI+QhovUJMhihXx/ubzrdeIa7eV6j1EIpZcHCoDq7IL4zIzgKWGSPa/+8SEKkjLFadEGGrsHj193fOrdkTG3g9XH8QXjPBbO7Trif1gmocclIjNgJEC7ikUb7Cnq4I+23YmL0u X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2019 09:44:59.8575 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d6a85ec6-43c7-4a7e-94b1-08d7636727ff X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR02MB6467 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently CCF clocks sre used in zynqmp dts. So there is no use of dtsi for fixed clock. Remove dtsi for fixed clock. Signed-off-by: Rajan Vaja --- arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 ----------------------------- 1 file changed, 213 deletions(-) delete mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi deleted file mode 100644 index 306ad21..0000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi +++ /dev/null @@ -1,213 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Clock specification for Xilinx ZynqMP - * - * (C) Copyright 2015 - 2018, Xilinx, Inc. - * - * Michal Simek - */ - -/ { - clk100: clk100 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - clk125: clk125 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clk200: clk200 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - clk250: clk250 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - }; - - clk300: clk300 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <300000000>; - }; - - clk600: clk600 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <600000000>; - }; - - dp_aclk: clock0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-accuracy = <100>; - }; - - dp_aud_clk: clock1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - clock-accuracy = <100>; - }; - - dpdma_clk: dpdma-clk { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <533000000>; - }; - - drm_clock: drm-clock { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <262750000>; - clock-accuracy = <0x64>; - }; -}; - -&can0 { - clocks = <&clk100 &clk100>; -}; - -&can1 { - clocks = <&clk100 &clk100>; -}; - -&fpd_dma_chan1 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan2 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan3 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan4 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan5 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan6 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan7 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan8 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan1 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan2 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan3 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan4 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan5 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan6 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan7 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan8 { - clocks = <&clk600>, <&clk100>; -}; - -&gem0 { - clocks = <&clk125>, <&clk125>, <&clk125>; -}; - -&gem1 { - clocks = <&clk125>, <&clk125>, <&clk125>; -}; - -&gem2 { - clocks = <&clk125>, <&clk125>, <&clk125>; -}; - -&gem3 { - clocks = <&clk125>, <&clk125>, <&clk125>; -}; - -&gpio { - clocks = <&clk100>; -}; - -&i2c0 { - clocks = <&clk100>; -}; - -&i2c1 { - clocks = <&clk100>; -}; - -&sata { - clocks = <&clk250>; -}; - -&sdhci0 { - clocks = <&clk200 &clk200>; -}; - -&sdhci1 { - clocks = <&clk200 &clk200>; -}; - -&spi0 { - clocks = <&clk200 &clk200>; -}; - -&spi1 { - clocks = <&clk200 &clk200>; -}; - -&uart0 { - clocks = <&clk100 &clk100>; -}; - -&uart1 { - clocks = <&clk100 &clk100>; -}; - -&usb0 { - clocks = <&clk250>, <&clk250>; -}; - -&usb1 { - clocks = <&clk250>, <&clk250>; -}; - -&watchdog0 { - clocks = <&clk250>; -}; -- 2.7.4