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[209.132.180.67]) by mx.google.com with ESMTP id c29si1476814ede.50.2019.11.07.05.47.24; Thu, 07 Nov 2019 05:47:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389292AbfKGNod (ORCPT + 99 others); Thu, 7 Nov 2019 08:44:33 -0500 Received: from cloudserver094114.home.pl ([79.96.170.134]:41233 "EHLO cloudserver094114.home.pl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730980AbfKGNoc (ORCPT ); Thu, 7 Nov 2019 08:44:32 -0500 Received: from 79.184.254.83.ipv4.supernova.orange.pl (79.184.254.83) (HELO kreacher.localnet) by serwer1319399.home.pl (79.96.170.134) with SMTP (IdeaSmtpServer 0.83.292) id 12ad8148bb496b03; Thu, 7 Nov 2019 14:44:30 +0100 From: "Rafael J. Wysocki" To: Mika Westerberg , Bjorn Helgaas Cc: Len Brown , Lukas Wunner , Keith Busch , Alex Williamson , Alexandru Gagniuc , Kai-Heng Feng , Paul Menzel , Nicholas Johnson , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 1/2] PCI: Introduce pcie_wait_for_link_delay() Date: Thu, 07 Nov 2019 14:44:29 +0100 Message-ID: <12302896.6UPH59xr33@kreacher> In-Reply-To: <20191107121847.24781-2-mika.westerberg@linux.intel.com> References: <20191107121847.24781-1-mika.westerberg@linux.intel.com> <20191107121847.24781-2-mika.westerberg@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thursday, November 7, 2019 1:18:46 PM CET Mika Westerberg wrote: > This is otherwise similar to pcie_wait_for_link() but allows passing > custom activation delay in milliseconds. > > Signed-off-by: Mika Westerberg No issues found: Reviewed-by: Rafael J. Wysocki > --- > drivers/pci/pci.c | 21 ++++++++++++++++++--- > 1 file changed, 18 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index ecc775793c3c..7083adc07f5c 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -4588,14 +4588,17 @@ static int pci_pm_reset(struct pci_dev *dev, int probe) > > return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); > } > + > /** > - * pcie_wait_for_link - Wait until link is active or inactive > + * pcie_wait_for_link_delay - Wait until link is active or inactive > * @pdev: Bridge device > * @active: waiting for active or inactive? > + * @delay: Delay to wait after link has become active (in ms) > * > * Use this to wait till link becomes active or inactive. > */ > -bool pcie_wait_for_link(struct pci_dev *pdev, bool active) > +static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, > + int delay) > { > int timeout = 1000; > bool ret; > @@ -4632,13 +4635,25 @@ bool pcie_wait_for_link(struct pci_dev *pdev, bool active) > timeout -= 10; > } > if (active && ret) > - msleep(100); > + msleep(delay); > else if (ret != active) > pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n", > active ? "set" : "cleared"); > return ret == active; > } > > +/** > + * pcie_wait_for_link - Wait until link is active or inactive > + * @pdev: Bridge device > + * @active: waiting for active or inactive? > + * > + * Use this to wait till link becomes active or inactive. > + */ > +bool pcie_wait_for_link(struct pci_dev *pdev, bool active) > +{ > + return pcie_wait_for_link_delay(pdev, active, 100); > +} > + > void pci_reset_secondary_bus(struct pci_dev *dev) > { > u16 ctrl; >