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From:   Fabio Estevam <festevam@gmail.com>
Date:   Thu, 7 Nov 2019 12:40:24 -0300
Message-ID: <CAOMZO5CiR7-YmAUggdt9rdZpNYKzQTFY5zGGGQ2k06Qc7pkg_Q@mail.gmail.com>
Subject: Re: [PATCH V2 1/4] ARM: dts: imx6sll: Update usdhc fallback
 compatible to support HS400 mode
To:     Anson Huang <Anson.Huang@nxp.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Sascha Hauer <kernel@pengutronix.de>,
        Andrey Smirnov <andrew.smirnov@gmail.com>,
        Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
        Marcel Ziswiler <marcel.ziswiler@toradex.com>,
        =?UTF-8?Q?S=C3=A9bastien_Szymanski?= 
        <sebastien.szymanski@armadeus.com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@lists.infradead.org>,
        NXP Linux Team <Linux-imx@nxp.com>
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Hi Anson,

On Wed, Nov 6, 2019 at 11:08 PM Anson Huang <Anson.Huang@nxp.com> wrote:
>
> The latest i.MX6SLL EVK board supports HS400 mode, update usdhc's

Since this is a dtsi patch, it is better not to mention a specific
board here in the commit log.

It would be better to say that unlike i.MX6SL, the i.MX6SLL SoC can
support HS400 mode, hence fsl,imx7d-usdhc should be used as compatible
string.

Regards,

Fabio Estevam
> fallback compatible to support HS400 mode by default.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> No changes.
> ---
>  arch/arm/boot/dts/imx6sll.dtsi | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
> index 85aa8bb..1c8101f 100644
> --- a/arch/arm/boot/dts/imx6sll.dtsi
> +++ b/arch/arm/boot/dts/imx6sll.dtsi
> @@ -698,7 +698,7 @@
>                         };
>
>                         usdhc1: mmc@2190000 {
> -                               compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
> +                               compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc";
>                                 reg = <0x02190000 0x4000>;
>                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
>                                 clocks = <&clks IMX6SLL_CLK_USDHC1>,
> @@ -712,7 +712,7 @@
>                         };
>
>                         usdhc2: mmc@2194000 {
> -                               compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
> +                               compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc";
>                                 reg = <0x02194000 0x4000>;
>                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
>                                 clocks = <&clks IMX6SLL_CLK_USDHC2>,
> @@ -726,7 +726,7 @@
>                         };
>
>                         usdhc3: mmc@2198000 {
> -                               compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
> +                               compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc";
>                                 reg = <0x02198000 0x4000>;
>                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
>                                 clocks = <&clks IMX6SLL_CLK_USDHC3>,
> --
> 2.7.4
>