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From:   Stefan Wahren <wahrenst@gmx.net>
Subject: [PATCH 2/4] ARM: dts: bcm2711: Enable PCIe controller
To:     Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
        Andrew Murray <andrew.murray@arm.com>,
        linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
        bcm-kernel-feedback-list@broadcom.com,
        linux-rpi-kernel@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org,
        Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Eric Anholt <eric@anholt.net>
Cc:     f.fainelli@gmail.com, phil@raspberrypi.org,
        linux-kernel@vger.kernel.org, mbrugger@suse.com,
        james.quinlan@broadcom.com
References: <20191106214527.18736-1-nsaenzjulienne@suse.de>
 <20191106214527.18736-3-nsaenzjulienne@suse.de>
Message-ID: <50074e33-17bf-d555-cbf6-4ec079472ecd@gmx.net>
Date:   Thu, 7 Nov 2019 18:44:00 +0100
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Hi Nicolas,

please move this patch behind the driver patches, which is the better orde=
r.

Am 06.11.19 um 22:45 schrieb Nicolas Saenz Julienne:
> This enables bcm2711's PCIe bus, wich is hardwired to a VIA Technologies
> XHCI USB 3.0 controller.
AFAIU this only applies to the Raspberry Pi 4, since the VIA is outside
of the SoC.
> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
> ---
>  arch/arm/boot/dts/bcm2711.dtsi | 47 ++++++++++++++++++++++++++++++++++
>  1 file changed, 47 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.=
dtsi
> index a9d84e28f245..c7b2e7b57da6 100644
> --- a/arch/arm/boot/dts/bcm2711.dtsi
> +++ b/arch/arm/boot/dts/bcm2711.dtsi
> @@ -288,6 +288,53 @@
>  		arm,cpu-registers-not-fw-configured;
>  	};
>
> +	scb {
> +		compatible =3D "simple-bus";
> +		#address-cells =3D <2>;
> +		#size-cells =3D <1>;
> +
> +		ranges =3D <0x0 0x7c000000  0x0 0xfc000000  0x03800000>,
> +			 <0x6 0x00000000  0x6 0x00000000  0x40000000>;
> +
> +		pcie_0: pcie@7d500000 {
> +			compatible =3D "brcm,bcm2711-pcie";
> +			reg =3D <0x0 0x7d500000 0x9310>;
> +			msi-controller;
> +			msi-parent =3D <&pcie_0>;
> +			#address-cells =3D <3>;
> +			#interrupt-cells =3D <1>;
> +			#size-cells =3D <2>;
> +			linux,pci-domain =3D <0>;
> +			brcm,enable-ssc;
> +			interrupts =3D <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names =3D "pcie", "msi";
> +			interrupt-map-mask =3D <0x0 0x0 0x0 0x7>;
> +			interrupt-map =3D <0 0 0 1 &gicv2 GIC_SPI 143
> +							IRQ_TYPE_LEVEL_HIGH
> +					 0 0 0 2 &gicv2 GIC_SPI 144
> +							IRQ_TYPE_LEVEL_HIGH
> +					 0 0 0 3 &gicv2 GIC_SPI 145
> +							IRQ_TYPE_LEVEL_HIGH
> +					 0 0 0 4 &gicv2 GIC_SPI 146
> +							IRQ_TYPE_LEVEL_HIGH>;
> +
> +			ranges =3D <0x02000000 0x0 0xf8000000 0x6 0x00000000
> +				  0x0 0x04000000>;
> +			/*
> +			 * The wrapper around the PCIe block has a bug
> +			 * preventing it from accessing beyond the first 3GB of
> +			 * memory. As the bus DMA mask is rounded up to the
> +			 * closest power of two of the dma-range size, we're
> +			 * forced to set the limit at 2GB. This can be
> +			 * harmlessly changed in the future once the DMA code
> +			 * handles non power of two DMA limits.
> +			 */
> +			dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000
> +				      0x0 0x80000000>;
In case this bug will ever be fixed, do you see this as a future proof
practical solution?
> +		};
> +	};
> +
>  	cpus: cpus {
>  		#address-cells =3D <1>;
>  		#size-cells =3D <0>;