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From:   Jingoo Han <jingoohan1@gmail.com>
To:     Dilip Kota <eswara.kota@linux.intel.com>,
        "gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>,
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        "robh@kernel.org" <robh@kernel.org>,
        "martin.blumenstingl@googlemail.com" 
        <martin.blumenstingl@googlemail.com>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
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        "andriy.shevchenko@intel.com" <andriy.shevchenko@intel.com>,
        "cheol.yong.kim@intel.com" <cheol.yong.kim@intel.com>,
        "chuanhua.lei@linux.intel.com" <chuanhua.lei@linux.intel.com>,
        "qi-ming.wu@intel.com" <qi-ming.wu@intel.com>,
        Han Jingoo <jingoohan1@gmail.com>
Subject: Re: [PATCH v5 3/3] PCI: artpec6: Configure FTS with dwc helper
 function
Thread-Topic: [PATCH v5 3/3] PCI: artpec6: Configure FTS with dwc helper
 function
Thread-Index: AQHVlFSCgoYxKfQji0+JDeSIjacZDaeANQQr
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Date:   Thu, 7 Nov 2019 21:03:46 +0000
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On 11/5/19, 10:44 PM, Dilip Kota wrote:
>=20
> Utilize DesugnWare helper functions to configure Fast Training

Nitpicking: Fix typo (DesugnWare --> DesignWare)

If possible, how about the following?
Utilize DesignWare --> Use DesignWare

Best regards,
Jingoo Han

> Sequence. Drop the respective code in the driver.
>
> Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
> ---
>  drivers/pci/controller/dwc/pcie-artpec6.c | 8 +-------
>  1 file changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/cont=
roller/dwc/pcie-artpec6.c
> index d00252bd8fae..02d93b8c7942 100644
> --- a/drivers/pci/controller/dwc/pcie-artpec6.c
> +++ b/drivers/pci/controller/dwc/pcie-artpec6.c
> @@ -51,9 +51,6 @@ static const struct of_device_id artpec6_pcie_of_match[=
];
>  #define ACK_N_FTS_MASK			GENMASK(15, 8)
>  #define ACK_N_FTS(x)			(((x) << 8) & ACK_N_FTS_MASK)
> =20
> -#define FAST_TRAINING_SEQ_MASK		GENMASK(7, 0)
> -#define FAST_TRAINING_SEQ(x)		(((x) << 0) & FAST_TRAINING_SEQ_MASK)
> -
>  /* ARTPEC-6 specific registers */
>  #define PCIECFG				0x18
>  #define  PCIECFG_DBG_OEN		BIT(24)
> @@ -313,10 +310,7 @@ static void artpec6_pcie_set_nfts(struct artpec6_pci=
e *artpec6_pcie)
>  	 * Set the Number of Fast Training Sequences that the core
>  	 * advertises as its N_FTS during Gen2 or Gen3 link training.
>  	 */
> -	val =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> -	val &=3D ~FAST_TRAINING_SEQ_MASK;
> -	val |=3D FAST_TRAINING_SEQ(180);
> -	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> +	dw_pcie_link_set_n_fts(pci, 180);
>  }
>
>  static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_=
pcie)
> --=20
> 2.11.0