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[209.132.180.67]) by mx.google.com with ESMTP id h13si2760607ejq.54.2019.11.07.18.07.52; Thu, 07 Nov 2019 18:08:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=AobIyWBW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728571AbfKHCGa (ORCPT + 99 others); Thu, 7 Nov 2019 21:06:30 -0500 Received: from mail-io1-f68.google.com ([209.85.166.68]:35625 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726281AbfKHCGa (ORCPT ); Thu, 7 Nov 2019 21:06:30 -0500 Received: by mail-io1-f68.google.com with SMTP id x21so4639454iol.2 for ; Thu, 07 Nov 2019 18:06:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=aSgW3A7RWyhsJj378/fhZw4bo/3lSZywb10x/TiQ6js=; b=AobIyWBWp8Z6LpdtKuyma3ufS/KNGQ+bmCTeW6cvoDC7nZ3SHSDceDgHKbyNh1AIwM CxX6yLM6gyuEKDxu8eYrOCBPuL58TvXko5kWxjv1YVWCJzzqo9G0qLEny5lAwy2u80JN +uoc4wzs5+DZjg+oVIZUomGzqkbJXUsZoz2/I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=aSgW3A7RWyhsJj378/fhZw4bo/3lSZywb10x/TiQ6js=; b=VOpkD0/S6wUaQJRTxjMGVHWUW4OMu8ic6eUKurAfyEUKqEff7VgdOvh6UBWvyU1GIs 9ObfetN3ZLy1IusxeZOax8DODsAELBcNw+770O42pXP2kVPzTYx2L86ceLYiVyH1/GWQ B5vJ57ZW2fS7J2uKmHgQWFsBlgk8ptsajDMuvwutBF58DE4mHetqE6QESdCveU3x0FGP 2uTQBYnWYzOMLsWTXkhJJwwoUjXF+B1fiL7f4alZMsQWmURDhS4EhIfHJLj73uXQq97w nhwITNlIeKqvqIdmKBSK2wRRnKjiy5Jjsgt6kYQm62KehS/EMatZfgMIcgniFNBpj/WH 3qRQ== X-Gm-Message-State: APjAAAXXh7db5GBJeK74Numtt1rbEpqAu6QacgYZbTXDEnImkeYOQphE dJC/+Lpvzc9SswRP/1fyDbgBNJtbF4GUiUXRCyEfMA== X-Received: by 2002:a02:58c8:: with SMTP id f191mr7652985jab.94.1573178789631; Thu, 07 Nov 2019 18:06:29 -0800 (PST) MIME-Version: 1.0 References: <20191014102308.27441-1-tdas@codeaurora.org> <20191014102308.27441-6-tdas@codeaurora.org> <20191029175941.GA27773@google.com> <20191031174149.GD27773@google.com> <20191107210606.E536F21D79@mail.kernel.org> In-Reply-To: <20191107210606.E536F21D79@mail.kernel.org> From: Rob Clark Date: Thu, 7 Nov 2019 18:06:19 -0800 Message-ID: Subject: Re: [PATCH v4 5/5] clk: qcom: Add Global Clock controller (GCC) driver for SC7180 To: Stephen Boyd Cc: Matthias Kaehlcke , Taniya Das , Michael Turquette , David Brown , Rajendra Nayak , linux-arm-msm , linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, LKML , devicetree@vger.kernel.org, robh@kernel.org, Rob Herring , Jordan Crouse , Jeykumar Sankaran , Sean Paul Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 7, 2019 at 1:06 PM Stephen Boyd wrote: > > Quoting Matthias Kaehlcke (2019-10-31 10:41:49) > > Hi Taniya, > > > > On Thu, Oct 31, 2019 at 04:59:26PM +0530, Taniya Das wrote: > > > Hi Matthias, > > > > > > Thanks for your comments. > > > > > > On 10/29/2019 11:29 PM, Matthias Kaehlcke wrote: > > > > Hi Taniya, > > > > > > > > On Mon, Oct 14, 2019 at 03:53:08PM +0530, Taniya Das wrote: > > > > > Add support for the global clock controller found on SC7180 > > > > > based devices. This should allow most non-multimedia device > > > > > drivers to probe and control their clocks. > > > > > > > > > > Signed-off-by: Taniya Das > > > > > > > > > > > v3 also had > > > > > > > > + [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, > > > > > > > > Removing it makes the dpu_mdss driver unhappy: > > > > > > > > [ 2.999855] dpu_mdss_enable+0x2c/0x58->msm_dss_enable_clk: 'iface' is not available > > > > > > > > because: > > > > > > > > mdss: mdss@ae00000 { > > > > ... > > > > > > > > => clocks = <&gcc GCC_DISP_AHB_CLK>, > > > > <&gcc GCC_DISP_HF_AXI_CLK>, > > > > <&dispcc DISP_CC_MDSS_MDP_CLK>; > > > > clock-names = "iface", "gcc_bus", "core"; > > > > }; > > > > > > > > > > The basic idea as you mentioned below was to move the CRITICAL clocks to > > > probe. The clock provider to return NULL in case the clocks are not > > > registered. > > > This was discussed with Stephen on v3. Thus I submitted the below patch. > > > clk: qcom: common: Return NULL from clk_hw OF provider. > > > > I see. My assumption was that the entire clock hierarchy should be registered, > > but Stephen almost certainly knows better :) > > > > > Yes it would throw these warnings, but no functional issue is observed from > > > display. I have tested it on the cheza board. > > > > The driver considers it an error (uses DEV_ERR to log the message) and doesn't > > handle other clocks when one is found missing. I'm not really famililar with > > the dpu_mdss driver, but I imagine this can have some side effects. Added some > > of the authors/contributors to cc. > > NULL is a valid clk pointer returned by clk_get(). What is the display > driver doing that makes it consider NULL an error? > do we not have an iface clk? I think the driver assumes we should have one, rather than it being an optional thing.. we could ofc change that BR, -R