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[209.132.180.67]) by mx.google.com with ESMTP id m9si3172266ejk.322.2019.11.07.22.37.36; Thu, 07 Nov 2019 22:38:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=C8RPxjnR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729816AbfKHGfo (ORCPT + 99 others); Fri, 8 Nov 2019 01:35:44 -0500 Received: from mail.kernel.org ([198.145.29.99]:57244 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725886AbfKHGfo (ORCPT ); Fri, 8 Nov 2019 01:35:44 -0500 Received: from kernel.org (unknown [104.132.0.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0262921882; Fri, 8 Nov 2019 06:35:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1573194943; bh=WtlyHdXzYR6zFb9CyoGvL3jaNaSQ59dn8PybAwn/UWk=; h=In-Reply-To:References:From:To:Cc:Subject:Date:From; b=C8RPxjnRf/hUxQQB3nIelAjN8AOWykVxtOvebXxVnI5p07Zuxo5v/ONyFiTk5YXNG 4lWRDtXRbzTaXbh9BvuFkk5NDeUMfupG5f8Afd8K8t5yLtRoB7c3LJOACpRIK4BmiF b7YZkHZhv9917xZyQUZ9VHTJMha+Z/awAExilEqw= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: References: <20191014102308.27441-1-tdas@codeaurora.org> <20191014102308.27441-6-tdas@codeaurora.org> <20191029175941.GA27773@google.com> <20191031174149.GD27773@google.com> <20191107210606.E536F21D79@mail.kernel.org> From: Stephen Boyd To: Rob Clark Cc: Matthias Kaehlcke , Taniya Das , Michael Turquette , David Brown , Rajendra Nayak , linux-arm-msm , linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, LKML , devicetree@vger.kernel.org, robh@kernel.org, Rob Herring , Jordan Crouse , Jeykumar Sankaran , Sean Paul Subject: Re: [PATCH v4 5/5] clk: qcom: Add Global Clock controller (GCC) driver for SC7180 User-Agent: alot/0.8.1 Date: Thu, 07 Nov 2019 22:35:42 -0800 Message-Id: <20191108063543.0262921882@mail.kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Rob Clark (2019-11-07 18:06:19) > On Thu, Nov 7, 2019 at 1:06 PM Stephen Boyd wrote: > > > > Quoting Matthias Kaehlcke (2019-10-31 10:41:49) > > > Hi Taniya, > > > > > > On Thu, Oct 31, 2019 at 04:59:26PM +0530, Taniya Das wrote: > > > > Hi Matthias, > > > > > > > > Thanks for your comments. > > > > > > > > On 10/29/2019 11:29 PM, Matthias Kaehlcke wrote: > > > > > Hi Taniya, > > > > > > > > > > On Mon, Oct 14, 2019 at 03:53:08PM +0530, Taniya Das wrote: > > > > > > Add support for the global clock controller found on SC7180 > > > > > > based devices. This should allow most non-multimedia device > > > > > > drivers to probe and control their clocks. > > > > > > > > > > > > Signed-off-by: Taniya Das > > > > > > > > > > > > > > v3 also had > > > > > > > > > > + [GCC_DISP_AHB_CLK] =3D &gcc_disp_ahb_clk.clkr, > > > > > > > > > > Removing it makes the dpu_mdss driver unhappy: > > > > > > > > > > [ 2.999855] dpu_mdss_enable+0x2c/0x58->msm_dss_enable_clk: 'if= ace' is not available > > > > > > > > > > because: > > > > > > > > > > mdss: mdss@ae00000 { > > > > > ... > > > > > > > > > > =3D> clocks =3D <&gcc GCC_DISP_AHB_CLK>, > > > > > <&gcc GCC_DISP_HF_AXI_CLK>, > > > > > <&dispcc DISP_CC_MDSS_MDP_CLK>; > > > > > clock-names =3D "iface", "gcc_bus", "core"; > > > > > }; > > > > > > > > > > > > > The basic idea as you mentioned below was to move the CRITICAL cloc= ks to > > > > probe. The clock provider to return NULL in case the clocks are not > > > > registered. > > > > This was discussed with Stephen on v3. Thus I submitted the below p= atch. > > > > clk: qcom: common: Return NULL from clk_hw OF provider. > > > > > > I see. My assumption was that the entire clock hierarchy should be re= gistered, > > > but Stephen almost certainly knows better :) > > > > > > > Yes it would throw these warnings, but no functional issue is obser= ved from > > > > display. I have tested it on the cheza board. > > > > > > The driver considers it an error (uses DEV_ERR to log the message) an= d doesn't > > > handle other clocks when one is found missing. I'm not really familil= ar with > > > the dpu_mdss driver, but I imagine this can have some side effects. A= dded some > > > of the authors/contributors to cc. > > > > NULL is a valid clk pointer returned by clk_get(). What is the display > > driver doing that makes it consider NULL an error? > > >=20 > do we not have an iface clk? I think the driver assumes we should > have one, rather than it being an optional thing.. we could ofc change > that I think some sort of AHB clk is always enabled so the plan is to just hand back NULL to the caller when they call clk_get() on it and nobody should be the wiser when calling clk APIs with a NULL iface clk. The common clk APIs typically just return 0 and move along. Of course, we'll also turn the clk on in the clk driver so that hardware can function properly, but we don't need to expose it as a clk object and all that stuff if we're literally just slamming a bit somewhere and never looking back. But it sounds like we can't return NULL for this clk for some reason? I haven't tried to track it down yet but I think Matthias has found it causes some sort of problem in the display driver.