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Subject: Re: [PATCH v7 10/11] iommu/vt-d: Support flushing more translation
 cache types
To:     Jacob Pan <jacob.jun.pan@linux.intel.com>,
        iommu@lists.linux-foundation.org,
        LKML <linux-kernel@vger.kernel.org>,
        Joerg Roedel <joro@8bytes.org>,
        David Woodhouse <dwmw2@infradead.org>,
        Alex Williamson <alex.williamson@redhat.com>,
        Jean-Philippe Brucker <jean-philippe@linaro.com>
Cc:     Yi Liu <yi.l.liu@intel.com>, "Tian, Kevin" <kevin.tian@intel.com>,
        Raj Ashok <ashok.raj@intel.com>,
        Christoph Hellwig <hch@infradead.org>,
        Lu Baolu <baolu.lu@linux.intel.com>,
        Jonathan Cameron <jic23@kernel.org>
References: <1571946904-86776-1-git-send-email-jacob.jun.pan@linux.intel.com>
 <1571946904-86776-11-git-send-email-jacob.jun.pan@linux.intel.com>
From:   Auger Eric <eric.auger@redhat.com>
Message-ID: <467e60cc-efb1-83d4-2dea-f6131a60428b@redhat.com>
Date:   Fri, 8 Nov 2019 17:18:10 +0100
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Hi Jacob,

On 10/24/19 9:55 PM, Jacob Pan wrote:
> When Shared Virtual Memory is exposed to a guest via vIOMMU, scalable
> IOTLB invalidation may be passed down from outside IOMMU subsystems.
> This patch adds invalidation functions that can be used for additional
> translation cache types.
>=20
> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> ---
>  drivers/iommu/dmar.c        | 46 +++++++++++++++++++++++++++++++++++++++=
++++++
>  drivers/iommu/intel-pasid.c |  3 ++-
>  include/linux/intel-iommu.h | 21 +++++++++++++++++----
>  3 files changed, 65 insertions(+), 5 deletions(-)
>=20
> diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c
> index 49bb7d76e646..0ce2d32ff99e 100644
> --- a/drivers/iommu/dmar.c
> +++ b/drivers/iommu/dmar.c
> @@ -1346,6 +1346,20 @@ void qi_flush_iotlb(struct intel_iommu *iommu, u16=
 did, u64 addr,
>  =09qi_submit_sync(&desc, iommu);
>  }
> =20
> +/* PASID-based IOTLB Invalidate */
> +void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u64 addr, u32 p=
asid,
> +=09=09unsigned int size_order, u64 granu, int ih)
> +{
> +=09struct qi_desc desc =3D {.qw2 =3D 0, .qw3 =3D 0};
> +
> +=09desc.qw0 =3D QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) |
> +=09=09QI_EIOTLB_GRAN(granu) | QI_EIOTLB_TYPE;
> +=09desc.qw1 =3D QI_EIOTLB_ADDR(addr) | QI_EIOTLB_IH(ih) |
> +=09=09QI_EIOTLB_AM(size_order);
> +
> +=09qi_submit_sync(&desc, iommu);
> +}
> +
>  void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
>  =09=09=09u16 qdep, u64 addr, unsigned mask)
>  {
> @@ -1369,6 +1383,38 @@ void qi_flush_dev_iotlb(struct intel_iommu *iommu,=
 u16 sid, u16 pfsid,
>  =09qi_submit_sync(&desc, iommu);
>  }
> =20
> +/* PASID-based device IOTLB Invalidate */
> +void qi_flush_dev_piotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
> +=09=09u32 pasid,  u16 qdep, u64 addr, unsigned size_order, u64 granu)
> +{
> +=09struct qi_desc desc;
> +
> +=09desc.qw0 =3D QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |
> +=09=09QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |
> +=09=09QI_DEV_IOTLB_PFSID(pfsid);
> +=09desc.qw1 =3D QI_DEV_EIOTLB_GLOB(granu);
> +
> +=09/* If S bit is 0, we only flush a single page. If S bit is set,
> +=09 * The least significant zero bit indicates the invalidation address
> +=09 * range. VT-d spec 6.5.2.6.
> +=09 * e.g. address bit 12[0] indicates 8KB, 13[0] indicates 16KB.
> +=09 */
> +=09if (!size_order) {
> +=09=09desc.qw0 |=3D QI_DEV_EIOTLB_ADDR(addr) & ~QI_DEV_EIOTLB_SIZE;
this is desc.qw1

With that fixed and the qi_flush_dev_piotlb init issue spotted by Lu,
feel free to add my

Reviewed-by: Eric Auger <eric.auger@redhat.com>

Thanks

Eric

> +=09} else {
> +=09=09unsigned long mask =3D 1UL << (VTD_PAGE_SHIFT + size_order);
> +=09=09desc.qw1 |=3D QI_DEV_EIOTLB_ADDR(addr & ~mask) | QI_DEV_EIOTLB_SIZ=
E;
> +=09}
> +=09qi_submit_sync(&desc, iommu);
> +}
> +
> +void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu,=
 int pasid)
> +{
> +=09struct qi_desc desc =3D {.qw1 =3D 0, .qw2 =3D 0, .qw3 =3D 0};
> +
> +=09desc.qw0 =3D QI_PC_PASID(pasid) | QI_PC_DID(did) | QI_PC_GRAN(granu) =
| QI_PC_TYPE;
> +=09qi_submit_sync(&desc, iommu);
> +}
>  /*
>   * Disable Queued Invalidation interface.
>   */
> diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
> index f846a907cfcf..6d7a701ef4d3 100644
> --- a/drivers/iommu/intel-pasid.c
> +++ b/drivers/iommu/intel-pasid.c
> @@ -491,7 +491,8 @@ pasid_cache_invalidation_with_pasid(struct intel_iomm=
u *iommu,
>  {
>  =09struct qi_desc desc;
> =20
> -=09desc.qw0 =3D QI_PC_DID(did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);
> +=09desc.qw0 =3D QI_PC_DID(did) | QI_PC_GRAN(QI_PC_PASID_SEL) |
> +=09=09QI_PC_PASID(pasid) | QI_PC_TYPE;
>  =09desc.qw1 =3D 0;
>  =09desc.qw2 =3D 0;
>  =09desc.qw3 =3D 0;
> diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
> index 6c74c71b1ebf..a25fb3a0ea5b 100644
> --- a/include/linux/intel-iommu.h
> +++ b/include/linux/intel-iommu.h
> @@ -332,7 +332,7 @@ enum {
>  #define QI_IOTLB_GRAN(gran) =09(((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFS=
ET-4))
>  #define QI_IOTLB_ADDR(addr)=09(((u64)addr) & VTD_PAGE_MASK)
>  #define QI_IOTLB_IH(ih)=09=09(((u64)ih) << 6)
> -#define QI_IOTLB_AM(am)=09=09(((u8)am))
> +#define QI_IOTLB_AM(am)=09=09(((u8)am) & 0x3f)
> =20
>  #define QI_CC_FM(fm)=09=09(((u64)fm) << 48)
>  #define QI_CC_SID(sid)=09=09(((u64)sid) << 32)
> @@ -350,16 +350,21 @@ enum {
>  #define QI_PC_DID(did)=09=09(((u64)did) << 16)
>  #define QI_PC_GRAN(gran)=09(((u64)gran) << 4)
> =20
> -#define QI_PC_ALL_PASIDS=09(QI_PC_TYPE | QI_PC_GRAN(0))
> -#define QI_PC_PASID_SEL=09=09(QI_PC_TYPE | QI_PC_GRAN(1))
> +/* PASID cache invalidation granu */
> +#define QI_PC_ALL_PASIDS=090
> +#define QI_PC_PASID_SEL=09=091
> =20
>  #define QI_EIOTLB_ADDR(addr)=09((u64)(addr) & VTD_PAGE_MASK)
>  #define QI_EIOTLB_IH(ih)=09(((u64)ih) << 6)
> -#define QI_EIOTLB_AM(am)=09(((u64)am))
> +#define QI_EIOTLB_AM(am)=09(((u64)am) & 0x3f)
>  #define QI_EIOTLB_PASID(pasid) =09(((u64)pasid) << 32)
>  #define QI_EIOTLB_DID(did)=09(((u64)did) << 16)
>  #define QI_EIOTLB_GRAN(gran) =09(((u64)gran) << 4)
> =20
> +/* QI Dev-IOTLB inv granu */
> +#define QI_DEV_IOTLB_GRAN_ALL=09=091
> +#define QI_DEV_IOTLB_GRAN_PASID_SEL=090
> +
>  #define QI_DEV_EIOTLB_ADDR(a)=09((u64)(a) & VTD_PAGE_MASK)
>  #define QI_DEV_EIOTLB_SIZE=09(((u64)1) << 11)
>  #define QI_DEV_EIOTLB_GLOB(g)=09((u64)g)
> @@ -655,8 +660,16 @@ extern void qi_flush_context(struct intel_iommu *iom=
mu, u16 did, u16 sid,
>  =09=09=09     u8 fm, u64 type);
>  extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
>  =09=09=09  unsigned int size_order, u64 type);
> +extern void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u64 addr=
,
> +=09=09=09u32 pasid, unsigned int size_order, u64 type, int ih);
>  extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 p=
fsid,
>  =09=09=09u16 qdep, u64 addr, unsigned mask);
> +
> +extern void qi_flush_dev_piotlb(struct intel_iommu *iommu, u16 sid, u16 =
pfsid,
> +=09=09=09u32 pasid, u16 qdep, u64 addr, unsigned size_order, u64 granu);
> +
> +extern void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64=
 granu, int pasid);
> +
>  extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iomm=
u);
> =20
>  extern int dmar_ir_support(void);
>=20