Received: by 2002:a25:31c3:0:0:0:0:0 with SMTP id x186csp2758664ybx; Fri, 8 Nov 2019 08:56:47 -0800 (PST) X-Google-Smtp-Source: APXvYqxTaBBfplCA8Xx+9Sb2/4WJJlMenkffYfThJrhA8iKCBLUr2/se10BMUweLNpBFVKNAqBqu X-Received: by 2002:a05:6402:70e:: with SMTP id w14mr11329004edx.95.1573232207689; Fri, 08 Nov 2019 08:56:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573232207; cv=none; d=google.com; s=arc-20160816; b=XbpFmbCAr275TFREi+4ZsqqCblmVml73CnVVDeaRMXsbosWN99IlP5VJbOk4KnvzjQ urmL7NibCsWCITGeAFt8FFjdlFhF8xASmZ2jnPIt2XwcTmqE4+aIiTIzHpZxbwIRpfE8 xvXLxeXnpkUGsRx0f8uP8yD8m/IlQiD7UTjhhXLXYw9D2MvDe7EsKb3A8Ntwwn2ZZh+L Ki1AF5wm+OPf0n0ZIDGyXS+Rf0DeDg/n5fUY8n34SOz0lpcQTHr3PG1p0qbH2TzCm/D4 d8oIy1Yl7L1nnHxfgYAd1M/Ks5C+Kraxrg+vI+UUbMVE9BFbbxQro4OUBtUFQRFr5c07 2SQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:dkim-signature; bh=oBlGL2ZT1qM/spp+v8OfQqLKwCRJpPtsexANJmTmPvA=; b=FZAev/nnNPdWsw0E5ydlbm17Y4q/6kw/qhMI76SQ9lYXlKmQ12hrhC2kZzSxAxWZv/ F/ZnKY/mZ9gj62Zjauxb+JzbtpVf0UJBYVIzjT12N+/9dayi6IDKQNiPsk4594YcgWt7 eUBTH4j/Zn8i4onk39lunTmhAYzKG0gLaopZJilCVtOkdh3rpAdKVRyFm1w8Qk0fG706 KyyjgNRQ5kCi3vjz7GL1w24z6eBfRYeXjHsPkg2PnuqdF43wezerzlEH6Dpmt04PgvCh J5TEBLkW9+z+IuaLxBAGJhGey83PSDQ4eLVVrKtaWffZW6NfytmuOO8hdxjcfUs3wgVr QH/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=ALZBV9VN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q15si4176859ejm.31.2019.11.08.08.56.23; Fri, 08 Nov 2019 08:56:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=ALZBV9VN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727516AbfKHQyf (ORCPT + 99 others); Fri, 8 Nov 2019 11:54:35 -0500 Received: from mail-io1-f65.google.com ([209.85.166.65]:42394 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726231AbfKHQyf (ORCPT ); Fri, 8 Nov 2019 11:54:35 -0500 Received: by mail-io1-f65.google.com with SMTP id g15so7075543iob.9 for ; Fri, 08 Nov 2019 08:54:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=oBlGL2ZT1qM/spp+v8OfQqLKwCRJpPtsexANJmTmPvA=; b=ALZBV9VNqthwC4XaKQWF9/+cuQdPrE6+x2xVO/S3DSHILymh5OMdjE/m5FYD0JbKBz LaIwUR3CoqB2Y3Fi88ga13AtQqlagoQ3HwKEVys0MRaPbWQM7/sOIzf/oBWHpxrmJki7 tjICYxKk/dsSORynQSmur0R/VsviWcGrbwP5E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=oBlGL2ZT1qM/spp+v8OfQqLKwCRJpPtsexANJmTmPvA=; b=AFMlMJpvEJ18j6JRDPGwO2q780K8GtpnaOxjkP8/vk9ZNfid6dsQCpu+T2olzwjOaS s4vhCliRmNyovr+qa3z6bBEnTcgF71tIsCC8d+7a+KRyQ7ggFzLWQMKccd9wUsJv229o rBSU6iIPoEZxgbfkLLGOJWncxO1+rxCfpyRrDr12tAwBEa5pwRq1wC3uOks0aQt8+7P5 pb97V/oGBaYI9Pl5Uwzr4zvOmdEtS7PwMp8rcVp18saSAp76luDhwF9aKhCKsjbpEb9u b4/Aw8sriLhOlOJTqpxBWdmhtLUNX1I7v59Lyq++hPJjZT6gaz1rVYFY+38o3iFcVkwN jixA== X-Gm-Message-State: APjAAAUgdokAqKxM/gudiIEWTUDZgAJ5/95REztwG3UB7gGXHyotVbdE RVIpk/nIooeZywgpNndrPq3pi8m90BEGV3Y2qVPeQQ== X-Received: by 2002:a6b:ee07:: with SMTP id i7mr11442996ioh.26.1573232074022; Fri, 08 Nov 2019 08:54:34 -0800 (PST) MIME-Version: 1.0 References: <20191014102308.27441-1-tdas@codeaurora.org> <20191014102308.27441-6-tdas@codeaurora.org> <20191029175941.GA27773@google.com> <20191031174149.GD27773@google.com> <20191107210606.E536F21D79@mail.kernel.org> <20191108063543.0262921882@mail.kernel.org> In-Reply-To: <20191108063543.0262921882@mail.kernel.org> From: Rob Clark Date: Fri, 8 Nov 2019 08:54:23 -0800 Message-ID: Subject: Re: [PATCH v4 5/5] clk: qcom: Add Global Clock controller (GCC) driver for SC7180 To: Stephen Boyd Cc: Matthias Kaehlcke , Taniya Das , Michael Turquette , David Brown , Rajendra Nayak , linux-arm-msm , linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, LKML , devicetree@vger.kernel.org, robh@kernel.org, Rob Herring , Jordan Crouse , Jeykumar Sankaran , Sean Paul Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 7, 2019 at 10:35 PM Stephen Boyd wrote: > > Quoting Rob Clark (2019-11-07 18:06:19) > > On Thu, Nov 7, 2019 at 1:06 PM Stephen Boyd wrote: > > > > > > Quoting Matthias Kaehlcke (2019-10-31 10:41:49) > > > > Hi Taniya, > > > > > > > > On Thu, Oct 31, 2019 at 04:59:26PM +0530, Taniya Das wrote: > > > > > Hi Matthias, > > > > > > > > > > Thanks for your comments. > > > > > > > > > > On 10/29/2019 11:29 PM, Matthias Kaehlcke wrote: > > > > > > Hi Taniya, > > > > > > > > > > > > On Mon, Oct 14, 2019 at 03:53:08PM +0530, Taniya Das wrote: > > > > > > > Add support for the global clock controller found on SC7180 > > > > > > > based devices. This should allow most non-multimedia device > > > > > > > drivers to probe and control their clocks. > > > > > > > > > > > > > > Signed-off-by: Taniya Das > > > > > > > > > > > > > > > > > v3 also had > > > > > > > > > > > > + [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, > > > > > > > > > > > > Removing it makes the dpu_mdss driver unhappy: > > > > > > > > > > > > [ 2.999855] dpu_mdss_enable+0x2c/0x58->msm_dss_enable_clk: 'iface' is not available > > > > > > > > > > > > because: > > > > > > > > > > > > mdss: mdss@ae00000 { > > > > > > ... > > > > > > > > > > > > => clocks = <&gcc GCC_DISP_AHB_CLK>, > > > > > > <&gcc GCC_DISP_HF_AXI_CLK>, > > > > > > <&dispcc DISP_CC_MDSS_MDP_CLK>; > > > > > > clock-names = "iface", "gcc_bus", "core"; > > > > > > }; > > > > > > > > > > > > > > > > The basic idea as you mentioned below was to move the CRITICAL clocks to > > > > > probe. The clock provider to return NULL in case the clocks are not > > > > > registered. > > > > > This was discussed with Stephen on v3. Thus I submitted the below patch. > > > > > clk: qcom: common: Return NULL from clk_hw OF provider. > > > > > > > > I see. My assumption was that the entire clock hierarchy should be registered, > > > > but Stephen almost certainly knows better :) > > > > > > > > > Yes it would throw these warnings, but no functional issue is observed from > > > > > display. I have tested it on the cheza board. > > > > > > > > The driver considers it an error (uses DEV_ERR to log the message) and doesn't > > > > handle other clocks when one is found missing. I'm not really famililar with > > > > the dpu_mdss driver, but I imagine this can have some side effects. Added some > > > > of the authors/contributors to cc. > > > > > > NULL is a valid clk pointer returned by clk_get(). What is the display > > > driver doing that makes it consider NULL an error? > > > > > > > do we not have an iface clk? I think the driver assumes we should > > have one, rather than it being an optional thing.. we could ofc change > > that > > I think some sort of AHB clk is always enabled so the plan is to just > hand back NULL to the caller when they call clk_get() on it and nobody > should be the wiser when calling clk APIs with a NULL iface clk. The > common clk APIs typically just return 0 and move along. Of course, we'll > also turn the clk on in the clk driver so that hardware can function > properly, but we don't need to expose it as a clk object and all that > stuff if we're literally just slamming a bit somewhere and never looking > back. > > But it sounds like we can't return NULL for this clk for some reason? I > haven't tried to track it down yet but I think Matthias has found it > causes some sort of problem in the display driver. > ok, I guess we can change the dpu code to allow NULL.. but what would the return be, for example on a different SoC where we do have an iface clk, but the clk driver isn't enabled? Would that also return NULL? I guess it would be nice to differentiate between those cases.. BR, -R