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[209.132.180.67]) by mx.google.com with ESMTP id y40si5102813edd.383.2019.11.08.09.43.12; Fri, 08 Nov 2019 09:43:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729773AbfKHRmH (ORCPT + 99 others); Fri, 8 Nov 2019 12:42:07 -0500 Received: from iolanthe.rowland.org ([192.131.102.54]:56406 "HELO iolanthe.rowland.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1726199AbfKHRmG (ORCPT ); Fri, 8 Nov 2019 12:42:06 -0500 Received: (qmail 4415 invoked by uid 2102); 8 Nov 2019 12:42:05 -0500 Received: from localhost (sendmail-bs@127.0.0.1) by localhost with SMTP; 8 Nov 2019 12:42:05 -0500 Date: Fri, 8 Nov 2019 12:42:05 -0500 (EST) From: Alan Stern X-X-Sender: stern@iolanthe.rowland.org To: Will Deacon cc: linux-kernel@vger.kernel.org, Yunjae Lee , SeongJae Park , "Paul E. McKenney" , Josh Triplett , Matt Turner , Ivan Kokshaysky , Richard Henderson , Peter Zijlstra , Michael Ellerman , "Michael S. Tsirkin" , Jason Wang , Arnd Bergmann , Joe Perches , Boqun Feng , , Subject: Re: [PATCH 10/13] tools/memory-model: Remove smp_read_barrier_depends() from informal doc In-Reply-To: <20191108170120.22331-11-will@kernel.org> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 8 Nov 2019, Will Deacon wrote: > 'smp_read_barrier_depends()' has gone the way of mmiowb() and so many > esoteric memory barriers before it. Drop the two mentions of this > deceased barrier from the LKMM informal explanation document. > > Signed-off-by: Will Deacon > --- > .../Documentation/explanation.txt | 26 +++++++++---------- > 1 file changed, 12 insertions(+), 14 deletions(-) > > diff --git a/tools/memory-model/Documentation/explanation.txt b/tools/memory-model/Documentation/explanation.txt > index 488f11f6c588..3050bf67b8d0 100644 > --- a/tools/memory-model/Documentation/explanation.txt > +++ b/tools/memory-model/Documentation/explanation.txt > @@ -1118,12 +1118,10 @@ maintain at least the appearance of FIFO order. > In practice, this difficulty is solved by inserting a special fence > between P1's two loads when the kernel is compiled for the Alpha > architecture. In fact, as of version 4.15, the kernel automatically > -adds this fence (called smp_read_barrier_depends() and defined as > -nothing at all on non-Alpha builds) after every READ_ONCE() and atomic > -load. The effect of the fence is to cause the CPU not to execute any > -po-later instructions until after the local cache has finished > -processing all the stores it has already received. Thus, if the code > -was changed to: > +adds this fence after every READ_ONCE() and atomic load on Alpha. The > +effect of the fence is to cause the CPU not to execute any po-later > +instructions until after the local cache has finished processing all > +the stores it has already received. Thus, if the code was changed to: > > P1() > { > @@ -1142,14 +1140,14 @@ READ_ONCE() or another synchronization primitive rather than accessed > directly. > > The LKMM requires that smp_rmb(), acquire fences, and strong fences > -share this property with smp_read_barrier_depends(): They do not allow > -the CPU to execute any po-later instructions (or po-later loads in the > -case of smp_rmb()) until all outstanding stores have been processed by > -the local cache. In the case of a strong fence, the CPU first has to > -wait for all of its po-earlier stores to propagate to every other CPU > -in the system; then it has to wait for the local cache to process all > -the stores received as of that time -- not just the stores received > -when the strong fence began. > +share this property: They do not allow the CPU to execute any po-later > +instructions (or po-later loads in the case of smp_rmb()) until all > +outstanding stores have been processed by the local cache. In the > +case of a strong fence, the CPU first has to wait for all of its > +po-earlier stores to propagate to every other CPU in the system; then > +it has to wait for the local cache to process all the stores received > +as of that time -- not just the stores received when the strong fence > +began. > > And of course, none of this matters for any architecture other than > Alpha. Acked-by: Alan Stern