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[209.132.180.67]) by mx.google.com with ESMTP id y38si5607884edb.87.2019.11.08.12.35.38; Fri, 08 Nov 2019 12:36:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@walle.cc header.s=mail2016061301 header.b="mTqgr/zo"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730159AbfKHUcP (ORCPT + 99 others); Fri, 8 Nov 2019 15:32:15 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:51819 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727015AbfKHUcO (ORCPT ); Fri, 8 Nov 2019 15:32:14 -0500 Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 7C2142335B; Fri, 8 Nov 2019 21:32:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1573245130; bh=6OR+Z5KfeblJ083HHiSeWa7E3WTa5ngobt1H+ZARamA=; h=From:To:Cc:Subject:Date:From; b=mTqgr/zojO6QfmKK52aioToRdveSx81BkWNxzWlpWzbqO0A39kt9/PpRamxsOy4Wh w8H02irm/xprzXQ38HU5sG30kBOqlYSokyWxvZr6AeqtehzJ2+UYtP+aHamUFwhJ5i zc2/RHwqa+HtNqKv6zg2oWzfLdJ3G/YL9NScWQfM= From: Michael Walle To: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Cc: Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , patches@opensource.cirrus.com, Charles Keepax , Michael Walle Subject: [PATCH v2] ASoC: wm8904: configure sysclk/FLL automatically Date: Fri, 8 Nov 2019 21:31:52 +0100 Message-Id: <20191108203152.19098-1-michael@walle.cc> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds a new mode WM8904_CLK_AUTO which automatically enables the FLL if a frequency different than the MCLK is set. These additions make the codec work with the simple-card driver in general and especially in systems where the MCLK doesn't match the required clock. Signed-off-by: Michael Walle --- changes since v1: - replaced second clk_get_rate() with mclk_freq Please note that the v1 patch might still be pending for moderator approval. sound/soc/codecs/wm8904.c | 72 ++++++++++++++++++++++++--------------- sound/soc/codecs/wm8904.h | 1 + 2 files changed, 45 insertions(+), 28 deletions(-) diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c index bcb3c9d5abf0..2a7d23a5daa8 100644 --- a/sound/soc/codecs/wm8904.c +++ b/sound/soc/codecs/wm8904.c @@ -1410,34 +1410,6 @@ static int wm8904_hw_params(struct snd_pcm_substream *substream, return 0; } - -static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id, - unsigned int freq, int dir) -{ - struct snd_soc_component *component = dai->component; - struct wm8904_priv *priv = snd_soc_component_get_drvdata(component); - - switch (clk_id) { - case WM8904_CLK_MCLK: - priv->sysclk_src = clk_id; - priv->mclk_rate = freq; - break; - - case WM8904_CLK_FLL: - priv->sysclk_src = clk_id; - break; - - default: - return -EINVAL; - } - - dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); - - wm8904_configure_clocking(component); - - return 0; -} - static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct snd_soc_component *component = dai->component; @@ -1824,6 +1796,50 @@ static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source, return 0; } +static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id, + unsigned int freq, int dir) +{ + struct snd_soc_component *component = dai->component; + struct wm8904_priv *priv = snd_soc_component_get_drvdata(component); + unsigned long mclk_freq; + int ret; + + switch (clk_id) { + case WM8904_CLK_AUTO: + mclk_freq = clk_get_rate(priv->mclk); + /* enable FLL if a different sysclk is desired */ + if (mclk_freq != freq) { + priv->sysclk_src = WM8904_CLK_FLL; + ret = wm8904_set_fll(dai, WM8904_FLL_MCLK, + WM8904_FLL_MCLK, + mclk_freq, freq); + if (ret) + return ret; + break; + } + clk_id = WM8904_CLK_MCLK; + /* fallthrough */ + + case WM8904_CLK_MCLK: + priv->sysclk_src = clk_id; + priv->mclk_rate = freq; + break; + + case WM8904_CLK_FLL: + priv->sysclk_src = clk_id; + break; + + default: + return -EINVAL; + } + + dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); + + wm8904_configure_clocking(component); + + return 0; +} + static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute) { struct snd_soc_component *component = codec_dai->component; diff --git a/sound/soc/codecs/wm8904.h b/sound/soc/codecs/wm8904.h index c1bca52f9927..de6340446b1f 100644 --- a/sound/soc/codecs/wm8904.h +++ b/sound/soc/codecs/wm8904.h @@ -10,6 +10,7 @@ #ifndef _WM8904_H #define _WM8904_H +#define WM8904_CLK_AUTO 0 #define WM8904_CLK_MCLK 1 #define WM8904_CLK_FLL 2 -- 2.20.1