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From:   Rajan Vaja <RAJANV@xilinx.com>
To:     Michael Tretter <m.tretter@pengutronix.de>
CC:     "mturquette@baylibre.com" <mturquette@baylibre.com>,
        "sboyd@kernel.org" <sboyd@kernel.org>,
        Michal Simek <michals@xilinx.com>,
        Jolly Shah <JOLLYS@xilinx.com>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Tejas Patel <TEJASP@xilinx.com>,
        Radhey Shyam Pandey <radheys@xilinx.com>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>
Subject: RE: [PATCH] clk: zynqmp: Add support for clock with
 CLK_DIVIDER_POWER_OF_TWO flag
Thread-Topic: [PATCH] clk: zynqmp: Add support for clock with
 CLK_DIVIDER_POWER_OF_TWO flag
Thread-Index: AQHVlUkv/SfvLcaY5E2Ze3HWYusTcKd//yyAgAXQRjA=
Date:   Mon, 11 Nov 2019 12:19:22 +0000
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Hi Michael,

Thanks for review.

> -----Original Message-----
> From: Michael Tretter <m.tretter@pengutronix.de>
> Sent: 07 November 2019 11:28 PM
> To: Rajan Vaja <RAJANV@xilinx.com>
> Cc: mturquette@baylibre.com; sboyd@kernel.org; Michal Simek
> <michals@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>; linux-clk@vger.kern=
el.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Tejas=
 Patel
> <TEJASP@xilinx.com>; Radhey Shyam Pandey <radheys@xilinx.com>;
> kernel@pengutronix.de
> Subject: Re: [PATCH] clk: zynqmp: Add support for clock with
> CLK_DIVIDER_POWER_OF_TWO flag
>=20
> EXTERNAL EMAIL
>=20
> On Thu, 07 Nov 2019 00:55:02 -0800, Rajan Vaja wrote:
> > From: Tejas Patel <tejas.patel@xilinx.com>
> >
> > Existing clock divider functions is not checking for
> > base of divider. So, if any clock divider is power of 2
> > then clock rate calculation will be wrong.
> >
> > Add support to calculate divider value for the clocks
> > with CLK_DIVIDER_POWER_OF_TWO flag.
> >
> > Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
> > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
> > Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
> > ---
> >  drivers/clk/zynqmp/divider.c | 36 +++++++++++++++++++++++++++++++-----
> >  1 file changed, 31 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.=
c
> > index d8f5b70d..ce63cf5 100644
> > --- a/drivers/clk/zynqmp/divider.c
> > +++ b/drivers/clk/zynqmp/divider.c
> > @@ -2,7 +2,7 @@
> >  /*
> >   * Zynq UltraScale+ MPSoC Divider support
> >   *
> > - *  Copyright (C) 2016-2018 Xilinx
> > + *  Copyright (C) 2016-2019 Xilinx
> >   *
> >   * Adjustable divider clock implementation
> >   */
> > @@ -44,9 +44,26 @@ struct zynqmp_clk_divider {
> >  };
> >
> >  static inline int zynqmp_divider_get_val(unsigned long parent_rate,
> > -                                      unsigned long rate)
> > +                                      unsigned long rate, u16 flags)
> >  {
> > -     return DIV_ROUND_CLOSEST(parent_rate, rate);
> > +     int up, down;
> > +     unsigned long up_rate, down_rate;
> > +
> > +     if (flags & CLK_DIVIDER_POWER_OF_TWO) {
> > +             up =3D DIV_ROUND_UP_ULL((u64)parent_rate, rate);
> > +             down =3D parent_rate / rate;
>=20
> Maybe use DIV_ROUND_DOWN_ULL()?
[Rajan] Ok. Will update in next version .

>=20
> > +
> > +             up =3D __roundup_pow_of_two(up);
> > +             down =3D __rounddown_pow_of_two(down);
> > +
> > +             up_rate =3D DIV_ROUND_UP_ULL((u64)parent_rate, up);
> > +             down_rate =3D DIV_ROUND_UP_ULL((u64)parent_rate, down);
> > +
> > +             return (rate - up_rate) <=3D (down_rate - rate) ? up : do=
wn;
>=20
> The calculation looks correct. Maybe there could be a common helper
> with the _div_round_closest() function?
[Rajan] _div_round_closest() is static function, and yes there is divider_r=
ound_rate_parent()
which ultimately uses _div_round_closest(), but it requires divider width w=
hich is not exposed
by firmware to driver.
=20
>=20
> > +
> > +     } else {
> > +             return DIV_ROUND_CLOSEST(parent_rate, rate);
> > +     }
> >  }
> >
> >  /**
> > @@ -78,6 +95,9 @@ static unsigned long zynqmp_clk_divider_recalc_rate(s=
truct
> clk_hw *hw,
> >       else
> >               value =3D div >> 16;
> >
> > +     if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
> > +             value =3D 1 << value;
>=20
> Not sure, but I think a small helper similar to _get_div() would help
> with the readability. Just hide the difference between the normal and
> power of two divisors behind some helper functions.
[Rajan] _git_dev() requires divider width which is not exposed
by firmware to user. So _get_div() can't used here. Also, there is no simil=
ar
helper available in linux. Correct me if I am missing something.

Thanks,
Rajan
>=20
> Michael
>=20
> > +
> >       if (!value) {
> >               WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
> >                    "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set=
\n",
> > @@ -120,10 +140,13 @@ static long zynqmp_clk_divider_round_rate(struct
> clk_hw *hw,
> >               else
> >                       bestdiv  =3D bestdiv >> 16;
> >
> > +             if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
> > +                     bestdiv =3D 1 << bestdiv;
> > +
> >               return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
> >       }
> >
> > -     bestdiv =3D zynqmp_divider_get_val(*prate, rate);
> > +     bestdiv =3D zynqmp_divider_get_val(*prate, rate, divider->flags);
> >
> >       if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_f=
rac)
> >               bestdiv =3D rate % *prate ? 1 : bestdiv;
> > @@ -151,7 +174,7 @@ static int zynqmp_clk_divider_set_rate(struct clk_h=
w
> *hw, unsigned long rate,
> >       int ret;
> >       const struct zynqmp_eemi_ops *eemi_ops =3D zynqmp_pm_get_eemi_ops=
();
> >
> > -     value =3D zynqmp_divider_get_val(parent_rate, rate);
> > +     value =3D zynqmp_divider_get_val(parent_rate, rate, divider->flag=
s);
> >       if (div_type =3D=3D TYPE_DIV1) {
> >               div =3D value & 0xFFFF;
> >               div |=3D 0xffff << 16;
> > @@ -160,6 +183,9 @@ static int zynqmp_clk_divider_set_rate(struct clk_h=
w
> *hw, unsigned long rate,
> >               div |=3D value << 16;
> >       }
> >
> > +     if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
> > +             div =3D __ffs(div);
> > +
> >       ret =3D eemi_ops->clock_setdivider(clk_id, div);
> >
> >       if (ret)