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[209.85.167.174]) by smtp.gmail.com with ESMTPSA id z13sm5118596otq.29.2019.11.11.10.11.45 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Nov 2019 10:11:45 -0800 (PST) Received: by mail-oi1-f174.google.com with SMTP id l20so12289218oie.10 for ; Mon, 11 Nov 2019 10:11:45 -0800 (PST) X-Received: by 2002:aca:1702:: with SMTP id j2mr240762oii.13.1573495904943; Mon, 11 Nov 2019 10:11:44 -0800 (PST) MIME-Version: 1.0 References: <20191108130123.6839-1-linux@rasmusvillemoes.dk> <20191108130123.6839-48-linux@rasmusvillemoes.dk> <14894529-a6bd-9b7e-eacc-06d5e49cc8e8@rasmusvillemoes.dk> In-Reply-To: <14894529-a6bd-9b7e-eacc-06d5e49cc8e8@rasmusvillemoes.dk> From: Li Yang Date: Mon, 11 Nov 2019 12:11:33 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 47/47] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE To: Rasmus Villemoes Cc: lkml , Scott Wood , linuxppc-dev , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Qiang Zhao Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 11, 2019 at 1:36 AM Rasmus Villemoes wrote: > > On 09/11/2019 00.48, Li Yang wrote: > > On Fri, Nov 8, 2019 at 7:05 AM Rasmus Villemoes > > wrote: > >> > >> There are also ARM and ARM64 based SOCs with a QUICC Engine, and the > >> core QE code as well as net/wan/fsl_ucc_hdlc and tty/serial/ucc_uart > >> has now been modified to not rely on ppcisms. > >> > >> So extend the architectures that can select QUICC_ENGINE, and add the > >> rather modest requirements of OF && HAS_IOMEM. > >> > >> The core code as well as the ucc_uart driver has been tested on an > >> LS1021A (arm), and it has also been tested that the QE code still > >> works on an mpc8309 (ppc). > >> > >> Signed-off-by: Rasmus Villemoes > >> --- > >> drivers/soc/fsl/qe/Kconfig | 3 ++- > >> 1 file changed, 2 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig > >> index cfa4b2939992..f1974f811572 100644 > >> --- a/drivers/soc/fsl/qe/Kconfig > >> +++ b/drivers/soc/fsl/qe/Kconfig > >> @@ -5,7 +5,8 @@ > >> > >> config QUICC_ENGINE > >> bool "QUICC Engine (QE) framework support" > >> - depends on FSL_SOC && PPC32 > >> + depends on OF && HAS_IOMEM > >> + depends on PPC32 || ARM || ARM64 || COMPILE_TEST > > > > Can you also add PPC64? It is also used on some PPC64 platforms > > (QorIQ T series). > > Sure, but if that's the only thing in the whole series, perhaps you > could amend it when applying instead of me sending all 47 patches again. Sure. I can do that. > > Should PPC32 || PPC64 be spelled PPC? Yes. That will be good. Regards, Leo