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From:   <Nicolas.Ferre@microchip.com>
To:     <Eugen.Hristev@microchip.com>, <mturquette@baylibre.com>,
        <sboyd@kernel.org>, <alexandre.belloni@bootlin.com>,
        <linux-clk@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>
CC:     <Ludovic.Desroches@microchip.com>
Subject: Re: [PATCH] clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value
Thread-Topic: [PATCH] clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value
Thread-Index: AQHVmJP4gkFvDXEvgEe8yodmIU1IZqeHWXyA
Date:   Tue, 12 Nov 2019 10:38:35 +0000
Message-ID: <67fc1d0b-5280-3bd6-10ba-0a303b4dc064@microchip.com>
References: <1573478913-19737-1-git-send-email-eugen.hristev@microchip.com>
In-Reply-To: <1573478913-19737-1-git-send-email-eugen.hristev@microchip.com>
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On 11/11/2019 at 14:28, Eugen Hristev - M18282 wrote:
> From: Eugen Hristev <eugen.hristev@microchip.com>
>=20
> Product datasheet recommends different values for UPLL and PLLA analog co=
ntrol
> register.
> Adapt accordingly.
>=20
> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

Best regards,
   Nicolas

> ---
>=20
> datasheet link http://ww1.microchip.com/downloads/en/DeviceDoc/SAM9X60-Da=
ta-Sheet-DS60001579A.pdf
> chapter 57.7.10 optimal setting of the PLLA and PLLUTMI
>=20
>   drivers/clk/at91/clk-sam9x60-pll.c | 8 ++++++--
>   1 file changed, 6 insertions(+), 2 deletions(-)
>=20
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sa=
m9x60-pll.c
> index 34b8178..dfb354a 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -25,7 +25,8 @@
>   #define		PMC_PLL_CTRL1_MUL_MSK		GENMASK(30, 24)
>  =20
>   #define PMC_PLL_ACR	0x18
> -#define		PMC_PLL_ACR_DEFAULT		0x1b040010UL
> +#define		PMC_PLL_ACR_DEFAULT_UPLL	0x12020010UL
> +#define		PMC_PLL_ACR_DEFAULT_PLLA	0x00020010UL
>   #define		PMC_PLL_ACR_UTMIVR		BIT(12)
>   #define		PMC_PLL_ACR_UTMIBG		BIT(13)
>   #define		PMC_PLL_ACR_LOOP_FILTER_MSK	GENMASK(31, 24)
> @@ -88,7 +89,10 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
>   	}
>  =20
>   	/* Recommended value for PMC_PLL_ACR */
> -	val =3D PMC_PLL_ACR_DEFAULT;
> +	if (pll->characteristics->upll)
> +		val =3D PMC_PLL_ACR_DEFAULT_UPLL;
> +	else
> +		val =3D PMC_PLL_ACR_DEFAULT_PLLA;
>   	regmap_write(regmap, PMC_PLL_ACR, val);
>  =20
>   	regmap_write(regmap, PMC_PLL_CTRL1,
>=20


--=20
Nicolas Ferre