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[31.17.61.94]) by smtp.gmail.com with ESMTPSA id r15sm224436wrc.5.2019.11.12.13.11.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Nov 2019 13:11:50 -0800 (PST) Date: Tue, 12 Nov 2019 22:11:48 +0100 From: Oliver Graute To: Fabio Estevam Cc: Shawn Guo , Marco Felsch , Neil Armstrong , Rob Herring , Mark Rutland , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , Andrey Smirnov , Manivannan Sadhasivam , Anson Huang , Marcel Ziswiler , =?iso-8859-1?Q?S=E9bastien?= Szymanski , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-kernel , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Subject: Re: [PATCH 3/3] dt-bindings: arm64: fsl: Add Variscite i.MX6UL compatibles Message-ID: <20191112211148.GF20321@ripley> References: <1573586526-15007-1-git-send-email-oliver.graute@gmail.com> <1573586526-15007-4-git-send-email-oliver.graute@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/11/19, Fabio Estevam wrote: > Hi Oliver > > On Tue, Nov 12, 2019 at 4:22 PM Oliver Graute wrote: > > > > Add the compatibles for Variscite i.MX6UL compatibles > > You missed your Signed-off-by tag. > > Also, you should remove arm64 from the Subject line as this is a 32-bit SoC :-) thx, you are right I messed thinks up. Because I also working with another 64-bit SoC in parallel. I'll fix it soon Best regards, Oliver