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From:   Stephen Boyd <sboyd@kernel.org>
To:     Rajan Vaja <rajan.vaja@xilinx.com>, dan.carpenter@oracle.com,
        gustavo@embeddedor.com, jolly.shah@xilinx.com,
        m.tretter@pengutronix.de, mark.rutland@arm.com,
        michal.simek@xilinx.com, mturquette@baylibre.com,
        nava.manne@xilinx.com, ravi.patel@xilinx.com, robh+dt@kernel.org,
        tejas.patel@xilinx.com
Cc:     linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        Rajan Vaja <rajan.vaja@xilinx.com>
Subject: Re: [PATCH 1/7] dt-bindings: clock: Add bindings for versal clock driver
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Date:   Tue, 12 Nov 2019 14:51:46 -0800
Message-Id: <20191112225147.7E59D21783@mail.kernel.org>
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Quoting Rajan Vaja (2019-11-12 05:16:14)
> diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml=
 b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> new file mode 100644
> index 0000000..da82f6a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bindings/clock/xlnx,versal-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx Versal clock controller
> +
> +maintainers:
> +  - Michal Simek <michal.simek@xilinx.com>
> +  - Jolly Shah <jolly.shah@xilinx.com>
> +  - Rajan Vaja <rajan.vaja@xilinx.com>
> +
> +description: |
> +  The clock controller is a h/w block of Xilinx versal clock tree. It re=
ads

hardware instead of h/w

> +  required input clock frequencies from the devicetree and acts as clock
> +  provider for all clock consumers of PS clocks. See clock_bindings.txt
> +  for more information on the generic clock bindings.

Please drop this last sentence about clock_bindings.txt

> +
> +properties:
> +  compatible:
> +    const: xlnx,versal-clk
> +
> +  "#clock-cells":
> +    const: 1
> +
> +  clocks:
> +    description: List of clock specifiers which are external input
> +      clocks to the given clock controller.
> +    minItems: 3
> +    maxItems: 3
> +    items:
> +      - description: ref clk
> +      - description: alternate ref clk
> +      - description: pl alternate ref clk

What is "pl"? Can you clarify?

> +
> +  clock-names:
> +    minItems: 3
> +    maxItems: 3
> +    items:
> +      - const: ref_clk
> +      - const: alt_ref_clk
> +      - const: pl_alt_ref_clk
> +
> +required:
> +  - compatible
> +  - "#clock-cells"
> +  - clocks
> +  - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    firmware {
> +      zynqmp_firmware: zynqmp-firmware {
> +        compatible =3D "xlnx,zynqmp-firmware";
> +        method =3D "smc";

Is there a way to say in the binding that this must be a child of a
xlnx,zynqmp-firmware node? That would be ideal so we can constrain this
to that location somehow.

> +        versal_clk: clock-controller {
> +          #clock-cells =3D <1>;
> +          compatible =3D "xlnx,versal-clk";
> +          clocks =3D <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;
> +          clock-names =3D "ref_clk", "alt_ref_clk", "pl_alt_ref_clk";
> +        };
> +      };
> +    };
> +...