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From:   Peng Fan <peng.fan@nxp.com>
To:     "sboyd@kernel.org" <sboyd@kernel.org>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
        "festevam@gmail.com" <festevam@gmail.com>,
        Abel Vesa <abel.vesa@nxp.com>
CC:     "kernel@pengutronix.de" <kernel@pengutronix.de>,
        dl-linux-imx <linux-imx@nxp.com>,
        Aisheng Dong <aisheng.dong@nxp.com>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Leonard Crestez <leonard.crestez@nxp.com>,
        Alice Guo <alice.guo@nxp.com>, Peng Fan <peng.fan@nxp.com>
Subject: [PATCH 2/2] clk: imx: composite-8m: use relaxed io api
Thread-Topic: [PATCH 2/2] clk: imx: composite-8m: use relaxed io api
Thread-Index: AQHVmglpFZP+G4Lm+0e0Ga/vcUI18Q==
Date:   Wed, 13 Nov 2019 10:02:09 +0000
Message-ID: <1573638817-4363-2-git-send-email-peng.fan@nxp.com>
References: <1573638817-4363-1-git-send-email-peng.fan@nxp.com>
In-Reply-To: <1573638817-4363-1-git-send-email-peng.fan@nxp.com>
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From: Peng Fan <peng.fan@nxp.com>

It is ok to use relaxed api here, no need to use stronger readl/writel

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-composite-8m.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-compo=
site-8m.c
index 20f7c91c03d2..513dc57483d0 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -31,14 +31,14 @@ static unsigned long imx8m_clk_composite_divider_recalc=
_rate(struct clk_hw *hw,
 	unsigned int prediv_value;
 	unsigned int div_value;
=20
-	prediv_value =3D readl(divider->reg) >> divider->shift;
+	prediv_value =3D readl_relaxed(divider->reg) >> divider->shift;
 	prediv_value &=3D clk_div_mask(divider->width);
=20
 	prediv_rate =3D divider_recalc_rate(hw, parent_rate, prediv_value,
 						NULL, divider->flags,
 						divider->width);
=20
-	div_value =3D readl(divider->reg) >> PCG_DIV_SHIFT;
+	div_value =3D readl_relaxed(divider->reg) >> PCG_DIV_SHIFT;
 	div_value &=3D clk_div_mask(PCG_DIV_WIDTH);
=20
 	return divider_recalc_rate(hw, prediv_rate, div_value, NULL,
@@ -104,13 +104,13 @@ static int imx8m_clk_composite_divider_set_rate(struc=
t clk_hw *hw,
=20
 	spin_lock_irqsave(divider->lock, flags);
=20
-	val =3D readl(divider->reg);
+	val =3D readl_relaxed(divider->reg);
 	val &=3D ~((clk_div_mask(divider->width) << divider->shift) |
 			(clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
=20
 	val |=3D (u32)(prediv_value  - 1) << divider->shift;
 	val |=3D (u32)(div_value - 1) << PCG_DIV_SHIFT;
-	writel(val, divider->reg);
+	writel_relaxed(val, divider->reg);
=20
 	spin_unlock_irqrestore(divider->lock, flags);
=20
--=20
2.16.4