Subject: Re: [PATCHSET] block: fix PIO cache coherency bug
From: James Bottomley <James.Bottomley@SteelEye.com>
To: Russell King <rmk+lkml@arm.linux.org.uk>
Cc: Tejun Heo <htejun@gmail.com>, axboe@suse.de, bzolnier@gmail.com,
       james.steward@dynamicratings.com, jgarzik@pobox.com,
       linux-kernel@vger.kernel.org
In-Reply-To: <20060113220215.GD31824@flint.arm.linux.org.uk>
References: <11371658562541-git-send-email-htejun@gmail.com>
	 <20060113220215.GD31824@flint.arm.linux.org.uk>
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Date: Fri, 13 Jan 2006 16:38:49 -0600
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On Fri, 2006-01-13 at 22:02 +0000, Russell King wrote:
> Unfortunately, as I previously explained, I'm not able to test this.
> The reason is that in order to reproduce the bug, you need a system
> with a VIVT write-back write-allocate cache.
> 
> Unfortunately, the few systems I have which have such a cache do not
> have IDE, SCSI nor SATA (not even PCMCIA.)  I suggest contacting the
> folk who reported the bug in the first instance.

Could someone explain (or give a reference to) the actual problem?  If
it's a cache coherency issue it should show up with VIPT arhictectures
as well as VIVT ones ... I have access to parisc systems (with SCSI),
which are VIPT.

James


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