Date: Fri, 13 Jan 2006 14:43:01 -0800 (PST)
Message-Id: <20060113.144301.09196399.davem@davemloft.net>
To: James.Bottomley@SteelEye.com
Cc: rmk+lkml@arm.linux.org.uk, htejun@gmail.com, axboe@suse.de,
       bzolnier@gmail.com, james.steward@dynamicratings.com, jgarzik@pobox.com,
       linux-kernel@vger.kernel.org
Subject: Re: [PATCHSET] block: fix PIO cache coherency bug
From: "David S. Miller" <davem@davemloft.net>
In-Reply-To: <1137191930.3365.96.camel@mulgrave>
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	<20060113220215.GD31824@flint.arm.linux.org.uk>
	<1137191930.3365.96.camel@mulgrave>
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From: James Bottomley <James.Bottomley@SteelEye.com>
Date: Fri, 13 Jan 2006 16:38:49 -0600

> Could someone explain (or give a reference to) the actual problem?  If
> it's a cache coherency issue it should show up with VIPT arhictectures
> as well as VIVT ones ... I have access to parisc systems (with SCSI),
> which are VIPT.

Not true, VIPT caches participate in cache coherency transactions
with the PCI host controller (and thus the PCI device), whereas
VIVT caches do not.

It does make a big difference, it's very hard to share datastructures
with a device concurrently accessing them (what we call PCI consistent
DMA mappings) on a VIVT cache.
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