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Cc:     linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, Orson Zhai <orsonzhai@gmail.com>,
        Baolin Wang <baolin.wang7@gmail.com>,
        Chunyan Zhang <zhang.lyra@gmail.com>,
        Xiaolong Zhang <xiaolong.zhang@unisoc.com>,
        Chunyan Zhang <chunyan.zhang@unisoc.com>
To:     Chunyan Zhang <chunyan.zhang@unisoc.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Rob Herring <robh+dt@kernel.org>
From:   Stephen Boyd <sboyd@kernel.org>
Subject: Re: [PATCH 1/5] clk: sprd: add gate for pll clocks
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Date:   Wed, 13 Nov 2019 14:15:28 -0800
Message-Id: <20191113221530.5CAD9206E3@mail.kernel.org>
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Quoting Chunyan Zhang (2019-10-25 04:13:34)
> diff --git a/drivers/clk/sprd/gate.c b/drivers/clk/sprd/gate.c
> index f59d1936b412..d8b480f852f3 100644
> --- a/drivers/clk/sprd/gate.c
> +++ b/drivers/clk/sprd/gate.c
> @@ -109,3 +120,11 @@ const struct clk_ops sprd_sc_gate_ops =3D {
>  };
>  EXPORT_SYMBOL_GPL(sprd_sc_gate_ops);
> =20
> +#define sprd_pll_sc_gate_unprepare sprd_sc_gate_disable

Why is there a redefine? Just use the function where it is.

> +
> +const struct clk_ops sprd_pll_sc_gate_ops =3D {
> +       .unprepare      =3D sprd_pll_sc_gate_unprepare,
> +       .prepare        =3D sprd_pll_sc_gate_prepare,
> +       .is_enabled     =3D sprd_gate_is_enabled,
> +};
> +EXPORT_SYMBOL_GPL(sprd_pll_sc_gate_ops);
> diff --git a/drivers/clk/sprd/gate.h b/drivers/clk/sprd/gate.h
> index dc352ea55e1f..598ce607ca0a 100644
> --- a/drivers/clk/sprd/gate.h
> +++ b/drivers/clk/sprd/gate.h
> @@ -14,16 +14,19 @@ struct sprd_gate {
>         u32                     enable_mask;
>         u16                     flags;
>         u16                     sc_offset;
> +       u32                     udelay;

Does the delay need to be 32 bits wide? Maybe a u8 or u16 will work?
Otherwise, make it an unsigned long please because the bit width doesn't
matter.