Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
MIME-Version: 1.0
References: <85a5484bc1f3dd53ce6f92700ad8b35f30a0b096.1571812029.git.baolin.wang@linaro.org>
 <20191114045005.GI952516@vkoul-mobl>
In-Reply-To: <20191114045005.GI952516@vkoul-mobl>
From:   "(Exiting) Baolin Wang" <baolin.wang@linaro.org>
Date:   Thu, 14 Nov 2019 13:33:30 +0800
Message-ID: <CAMz4kuL8by3BzFYocO5eZ0YdA5aUoCjybMHwDC4HsVSzr1Pt6Q@mail.gmail.com>
Subject: Re: [PATCH] dmaengine: sprd: Add wrap address support for link-list mode
To:     Vinod Koul <vkoul@kernel.org>
Cc:     Orson Zhai <orsonzhai@gmail.com>,
        Chunyan Zhang <zhang.lyra@gmail.com>,
        Dan Williams <dan.j.williams@intel.com>,
        LKML <linux-kernel@vger.kernel.org>, dmaengine@vger.kernel.org,
        eric.long@unisoc.com, baolin.wang7@gmail.com
Content-Type: text/plain; charset="UTF-8"
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On Thu, 14 Nov 2019 at 12:50, Vinod Koul <vkoul@kernel.org> wrote:
>
> On 23-10-19, 14:31, Baolin Wang wrote:
> > From: Eric Long <eric.long@unisoc.com>
> >
> > The Spreadtrum Audio compress offload mode will use 2-stage DMA transfer
> > to save power. That means we can request 2 dma channels, one for source
> > channel, and another one for destination channel. Once the source channel's
> > transaction is done, it will trigger the destination channel's transaction
> > automatically by hardware signal.
> >
> > In this case, the source channel will transfer data from IRAM buffer to
> > the DSP fifo to decoding/encoding, once IRAM buffer is empty by transferring
> > done, the destination channel will start to transfer data from DDR buffer
> > to IRAM buffer. Since the destination channel will use link-list mode to
> > fill the IRAM data, and IRAM buffer is allocated by 32K, and DDR buffer
> > is larger to 2M, that means we need lots of link-list nodes to do a cyclic
> > transfer, instead wasting lots of link-list memory, we can use wrap address
> > support to reduce link-list node number, which means when the transfer
> > address reaches the wrap address, the transfer address will jump to the
> > wrap_to address specified by wrap_to register, and only 2 link-list nodes
> > can do a cyclic transfer to transfer data from DDR to IRAM.
> >
> > Thus this patch adds wrap address to support this case.
>
> This fails to apply, can you please rebase and resend!

Sure, sorry for the trouble. Will rebase and resend. Thanks.

-- 
Baolin Wang
Best Regards