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Date:   Wed, 13 Nov 2019 23:45:10 -0800 (PST)
From:   Paul Walmsley <paul.walmsley@sifive.com>
To:     Christoph Hellwig <hch@lst.de>
cc:     Palmer Dabbelt <palmer@sifive.com>,
        Damien Le Moal <damien.lemoal@wdc.com>,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        Anup Patel <anup@brainfault.org>
Subject: Re: [PATCH 09/12] riscv: clear the instruction cache and all registers
 when booting
In-Reply-To: <20191028121043.22934-10-hch@lst.de>
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References: <20191028121043.22934-1-hch@lst.de> <20191028121043.22934-10-hch@lst.de>
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On Mon, 28 Oct 2019, Christoph Hellwig wrote:

> When we get booted we want a clear slate without any leaks from previous
> supervisors or the firmware.  Flush the instruction cache and then clear
> all registers to known good values.  This is really important for the
> upcoming nommu support that runs on M-mode, but can't really harm when
> running in S-mode either.  Vaguely based on the concepts from opensbi.
> 
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> Reviewed-by: Anup Patel <anup@brainfault.org>

Thanks, queued for v5.5-rc1.

- Paul